49th week of 2009 patent applcation highlights part 23 |
Patent application number | Title | Published |
20090295371 | ACTUATOR/WEDGE IMPROVEMENTS TO EMBEDDED METER SWITCH - Disclosed is a wedge shaped actuator device configured to provide separation of spring supported electrical contacts in an electrical switch. The wedge is configured with dual contour sides to maximize transfer of energy from a drive solenoid to the contact carrying springs. Portions of the wedge are relieved to allow for uninhibited movement of the wedge over side surfaces of the contact carrying springs to avoid digging in of any rough materials from the side edges of the spring as may be occasioned due to stamping techniques used to form the springs. | 2009-12-03 |
20090295372 | Nanoscopic electrode molecular probes - The present invention relates to a method and apparatus for enhancing the electron transport property measurements of a molecule when the molecule is placed between chemically functionalized carbon-based nanoscopic electrodes to which a suitable voltage bias is applied. The invention includes selecting a dopant atom for the nanoscopic electrodes, the dopant atoms being chemically similar to atoms present in the molecule, and functionalizing the outer surface and terminations of the electrodes with the dopant atoms. | 2009-12-03 |
20090295373 | INTEGRATED CIRCUIT WITH TRACKING LOGIC - An integrated circuit including an amplifier and a first circuit. The amplifier is configured to receive a sensed signal and provide an amplified signal. The first circuit is configured to track a first signal that is based on the amplified signal. The first circuit includes a first comparator, tracking logic and a first digital to analog converter. The first comparator is configured to respond to a second signal that is based on the first signal and provide a comparator output signal. The tracking logic is configured to receive the comparator output signal and update a digital output. The first digital to analog converter is configured to receive the digital output and provide a tracking signal that is summed with the first signal to provide the second signal. | 2009-12-03 |
20090295374 | Sensor - A sensor according to the invention has a U-shaped magnet having a pair of opposing portions spaced apart from each other, forming a flux-free region between the pair of opposing portions. A Hall element varies an output voltage according to the density of passing flux. A spacer regulates the positional relationship between the Hall element and the U-shaped magnet such that the Hall element is positioned in the flux-free region of the U-shaped magnet and a housing covers the spacer. | 2009-12-03 |
20090295375 | Rotation sensor - A rotation sensor for detecting rotation of an object includes a semiconductor substrate, a vertical Hall element, and a magnetoresistive element. The vertical Hall element is formed in the semiconductor substrate to detect a magnetic field parallel to a surface of the semiconductor substrate. The vertical Hall element outputs a detection signal corresponding to the detected magnetic field. The magnetoresistive element is formed on the surface of the semiconductor substrate and has a resistance value changing with strength of the magnetic field. The magnetoresistive element outputs a resistance signal corresponding to the resistance value. The rotation is detected based on the detection signal and the resistance signal. | 2009-12-03 |
20090295376 | MAGNETIC ODOMETER WITH DIRECTION INDICATOR SYSTEMS AND METHODS - Systems and methods for determining a directional movement of an object such as a wheeled vehicle. The system includes a magnet having a north pole and a south pole mounted to the object, a single magnetic sensor positioned such that the sensor can individually detect each magnetic pole as the object moves, the sensor configured to produce a first characteristic signal when a north pole is detected and a second characteristic signal when a south pole is detected, and a processing device in signal communication with the sensor, the processing device configured to determine a directional movement of the object based on a configuration of a signal doublet that includes the first and second characteristic signals. The methods include sensing the north and south poles as they pass the magnetic sensor and determining a direction based on an order in which the north and south poles are sensed. | 2009-12-03 |
20090295377 | Contactless position sensor for vehicle - A position sensor has opposed parallel flux concentrators with a gap between them, and permanent magnets are disposed between the concentrators at the ends of the concentrators in the gap. A magnetic sense element is disposed in the gap between the magnets. The magnets with flux concentrators do not move relative to each other, and may be coupled to a moving part whose position is sought to be measured, whereas the sense element may be coupled to a stationary part. | 2009-12-03 |
20090295378 | CONFINED FIELD MAGNET SYSTEM AND METHOD - A system and method of generating a magnetic field that is uniform in magnitude and direction may generally restrict the field from expanding away from a longitudinal axis. In some instances, such a magnetic field may be controllable in magnitude and direction. In accordance with some embodiments, a generated magnetic field may be selectively confined to a predetermined three-dimensional space. | 2009-12-03 |
20090295379 | ELECTROMAGNETIC FIELD MEASURING APPARATUS AND METHOD THEREFOR - A plate conductor and at least three columnar conductors erected on the plate conductor are provided. At the same time when an electric field is measured by the plate conductor, two components of a magnetic field at the same measurement points as those at which the electric field is measured are measured by a loop formed by the plate conductor and the columnar conductors at the same time. As a result, three components of an electromagnetic field formed of one component of the electric field and two components of the magnetic field are measured at the same point, with high sensitivity, and at the same time. | 2009-12-03 |
20090295380 | CIRCUIT THAT PROVIDES OUTPUT VOLTAGES IN A HOMOGENOUS MAGNETIC FIELD - A circuit including Hall plates and an amplifier. The Hall plates are configured to provide Hall voltages in a homogenous magnetic field such that a first Hall plate has a first positive voltage and a first negative voltage and a second Hall plate has a second positive voltage and a second negative voltage. The amplifier is configured to receive the Hall voltages and provide a first output voltage that corresponds to the first positive voltage and the second positive voltage and a second output voltage that corresponds to the first negative voltage and the second negative voltage. | 2009-12-03 |
20090295381 | MAGNETIC SENSOR INTEGRATED CIRCUIT DEVICE AND METHOD - An sensor includes a substrate with a magnetic field sensor mounted on the substrate. The magnetic field sensor has a first surface defining a plane. A magnetic flux conducting member has a second surface that is not parallel to the first surface. A non-magnetic member is situated between the magnetic field sensor and the magnetic flux conducting member. | 2009-12-03 |
20090295382 | METHODS AND SYSTEMS FOR MAGNETIC FIELD SENSING - One embodiment relates to a sensor. The sensor includes a first magnet having a first surface and a second magnet having a second surface. A differential sensing element extends alongside the first and second surfaces. The differential sensing element includes a first sensing element and a second sensing element. In addition, a layer of ferromagnetic or paramagnetic material runs between the first and second magnets and spaces the first and second magnets from one another. Other apparatuses and methods are also set forth. | 2009-12-03 |
20090295383 | Wireless Biliary Stent System with Wishbone-Array Resonant Magnetoelastic Sensor and Conformal Magnetic Layer - A stent and a magnetoelastic resonant sensor are provided for sensor a physical characteristic in a bodily vessel or cavity. External coils interact with the sensor to induce a resonance that is responsive to the physical characteristic, such that the device may wirelessly measure physical characteristics such as mass loading effects and viscosity changes due to progression of pathology in implanted stents and stent grafts. The sensor may be fashioned from a magnetoelastic material and may be integrated near the inner sidewall of the stent. The sensor may take on a complex patterned shape to enhance the sensitivity and flexibility of the sensor structure. When the sensor is interrogated with a time-varying magnetic field, the sensor will mechanically vibrate and generate a magnetic flux which is maximum at a resonant characteristic determined by the mass load on the sensor and the viscosity of the fluid surrounding the sensor. By correlating the measured resonant characteristic to the mass load and viscosity, the pathological state in and around the stent can be determined. | 2009-12-03 |
20090295384 | Magnetic field sensor and electrical current sensor therewith - A magnetic field sensor comprises a magnetic field sensing cell and a magnetic shield comprising at least two parts separated by an air-gap and surrounding the magnetic field sensing cell positioned in a cavity of the magnetic shield. | 2009-12-03 |
20090295385 | Magneto Sensor System and Method of Use - Instruments, systems and methods for using the instrument and systems are disclosed, where the systems include a magneto sensor, such as a superconducting quantum interference device (“SQUID”) and are designed to detect changes in a magnetic field in an animal including a human. | 2009-12-03 |
20090295386 | POSITION DETECTION SYSTEM - A position detection system that does not require calibration measurement to be performed in advance and reduces the work required for detecting a position and so on is provided. The provided position detection system includes a device having a magnetic inductance coil; a drive coil that has a position-calculating frequency near a resonant frequency of the magnetic inductance coil and generates an alternating magnetic field which acts on the magnetic inductance coil; a plurality of magnetic-field sensors that is disposed outside the operating range of the device and detects an induced magnetic field generated by the magnetic inductance coil; amplitude-component detection section for detecting amplitude components whose phase is substantially orthogonal to the alternating magnetic field from the outputs of the magnetic sensors acquired by the plurality of magnetic sensors; and position analyzing section for calculating at least one of a position and an orientation of the device on the basis of the amplitude components. | 2009-12-03 |
20090295387 | Shear Wave Generation System For Medical Imaging - A system is configured to produce a stress on a subject while performing a magnetic resonance elastography scan in a magnetic resonance imaging (MRI) system. The system includes an active driver operable to produce an energy configured for a magnetic resonance elastography (MRE) process. A passive actuator is configured to be positioned in the MRI system and to be coupled to the subject. The system includes a tube coupling the active driver to the passive actuator to deliver the energy produced by the active driver to the passive actuator, and a strap coupled to the passive actuator. The strap is configured to be disposed around the subject. The strap includes a substantially inelastic material configured to convert the energy delivered to the passive actuator from the tube into shear waves with the subject for use in the MRE process. | 2009-12-03 |
20090295388 | HYBRID AUTOMATIC TUNING/MATCHING FOR NMR PROBES - Remote adjustment of a selected one of a plurality of adjustable NMR probe circuit components is achieved with a plurality of selectable linear actuators, the selected one of which urges a platen against a respective driven gear, azimuthally locked to its shaft, to displace it axially along that shaft. When the driven gear engages a driving gear a single driving motor is energized and controlled to effect the desired adjustment. | 2009-12-03 |
20090295389 | MAGNETIC FIELD PROBE AND METHOD FOR MANUFACTURING THE SAME - A magnetic field probe comprises a sample ( | 2009-12-03 |
20090295390 | LOW FIELD ELECTRON PARAMAGNETIC RESONANCE IMAGING WITH SQUID DETECTION - In one embodiment, a flux transformer with a gradiometer pickup coil is magnetically coupled to a SQUID, and a SQUID array amplifier comprising a plurality of SQUIDs, connected in series, is magnetically coupled to the output of the SQUID. Other embodiments are described and claimed. | 2009-12-03 |
20090295391 | Combined Electromagnetic Sensor and Magnetometer - A combined electromagnetic and magnetometer detection system for detecting objects. The system includes a primary electromagnetic transmitter for generating a primary magnetic field; an electromagnetic sensor for sensing secondary magnetic fields generated by a target region subjected to the primary magnetic field; a magnetometer sensor substantially centered at a center of the primary magnetic field; a compensation transmitter for generating a compensating magnetic field that substantially negates the primary magnetic field across the magnetometer sensor; and a signal generator electrically connected to the primary electromagnetic transmitter and the compensation transmitter for driving the transmitters to generate the primary magnetic field and the compensating magnetic field, respectively. | 2009-12-03 |
20090295392 | Resistivity Imager in Non-Conductive Mud for LWD and Wireline Applications - An apparatus, method and computer-readable medium for imaging an earth formation. A downhole assembly having a resistivity sensor is conveyed in a borehole penetrating the earth formation. The resistivity sensor includes a plurality of antenna coils arranged along a radial line that is substantially perpendicular to a longitudinal axis of the downhole assembly and configured to obtain measurements of a resistivity property of the earth formation. A processor images the earth formation using the obtained measurements. | 2009-12-03 |
20090295393 | Octupole Induction Sensors for Resistivity Imaging in Non-Conductive Muds - The present disclosure provides a method and apparatus for performing resistivity measurements of a borehole wall using a transverse octupole sensor. The sensor may be a resistivity sensor. Higher resolution is obtained with an octupole sensor than with lower-order-pole sensors. For the resistivity case, the ratio of dual-frequency measurements has reduced sensitivity to standoff. | 2009-12-03 |
20090295394 | SENSOR CABLE FOR ELECTROMAGNETIC SURVEYING - A sensor cable for surveying. The sensor cable may comprise at least one pair of current sensor electrodes and an amplifier. The current sensor electrodes may be disposed along opposite sides of the sensor cable. The current sensor electrodes may be configured to detect current in an electromagnetic field transverse to an inline direction of the sensor cable. The amplifier may be configured to amplify the current in the electromagnetic field for detection by the electrode pair. | 2009-12-03 |
20090295395 | STORAGE BATTERY AND BATTERY TESTER - A storage battery is provided which has a first and second post for electrically coupling to an electrical system. A test plug is provided for use in coupling the storage battery to an electronic battery tester. In another aspect, a battery tester is provided having a plug configured to couple to a test plug of a storage battery for use in performing an electronic battery test on the storage battery. | 2009-12-03 |
20090295396 | Assembled battery monitoring apparatus, method for detecting wiring disconnection of assembled battery, and assembled battery system - An assembled battery monitoring device that detects presence of disconnection in wiring pulled from an assembled battery in which a plurality of electric cells are connected in series. The electric cells are connected respectively in parallel to auxiliary current channels each having a setting resistance value, and the presence of the disconnection in the wiring is detected based on a detection voltage when the switching device for auxiliary current channel is turned to the closed state. | 2009-12-03 |
20090295397 | Systems and Methods for Determining Battery Parameters Following Active Operation of the Battery - When the load of a battery powered device is removed or significantly reduced, the voltage response may be recorded or analyzed in real time. The parameters of a battery's equivalent circuit can be found by fitting recorded or real time voltage response to a model function. The model function may describe the equivalent circuit voltage response to the load transition through equivalent circuit parameters. The model function may account for a duration of a load application prior to a transition as well as values of the load before and after the transition. Response of battery voltage to load application or load release is time dependent. Modeling of this time dependence can provide significant advantages in fuel gauging implementation, for example, to significantly reduce the waiting time before measured voltages can be used for state of charge (SOC) correlation and to improve the accuracy of the prediction of run-time for devices that drain a battery in short high-current pulses. | 2009-12-03 |
20090295398 | VOLTAGE DETECTING DEVICE FOR BATTERY MODULES - A voltage detecting device for battery modules can reduce the difference in frequency response of an anti-aliasing filter for each battery module whose voltage is measured, and provide an accurate voltage measurement. The voltage detecting device for battery modules includes a plurality of switches connected to battery modules constituting a secondary battery, resistors having an equal resistance value, and a filter composed of capacitors having equal capacitance and being disposed between the battery modules and the switches. The capacitors are divided into a first capacitor group and a second capacitor group which are symmetrical at the center of the secondary battery. The first capacitor group is on the positive terminal side of the second battery. The second capacitor is on the negative terminal side of the secondary battery. | 2009-12-03 |
20090295399 | On-vehicle battery condition estimation device - A battery condition estimation device estimates a pre-restart voltage drop amount ΔVjh+ΔVbn of a battery mounted to a vehicle during period T | 2009-12-03 |
20090295400 | Electrostatic partricle sensor - An electrostatic particle sensor for sensing particles in exhaust gases includes: a lateral surface electrode having an effective flow volume, a gas flow to be tested flowing through it; an inner electrode situated inside the lateral surface electrode; and a voltage source which is in an electrically conducting connection with both electrodes. A potential which is dependent on the gas flow rate per time unit through the effective flow volume is impressed upon the voltage source. | 2009-12-03 |
20090295401 | LEAK DETECTING CIRCUIT - A leak detecting circuit includes: a current path having one end connected to a conductor housing a device supplied with a direct-current voltage from a direct-current power source, and having another end connected to a negative electrode of the direct-current power source; the current path including a limiting resistance for limiting a current, a switch element having a first electrode, a second electrode, and a control electrode, conduction between the first electrode and the second electrode being controlled, a detecting resistance for detecting a current flowing through the current path, and a variable direct-current power source allowing a plurality of leak detecting reference voltages for detecting a leak to be selected, and having a negative electrode connected to the negative electrode of the direct-current power source; an amplifier for amplifying a voltage across the detecting resistance; and a constant-voltage circuit for making constant a potential difference between a voltage of the control electrode of the switch element and a voltage of a positive electrode of the variable direct-current power source; wherein a leak between the conductor and the direct-current power source is detected on a basis of the voltage across the detecting resistance, the voltage across the detecting resistance being amplified by the amplifier. | 2009-12-03 |
20090295402 | VOLTAGE ISLAND PERFORMANCE/LEAKAGE SCREEN MONITOR FOR IP CHARACTERIZATION - A method is provided for characterizing performance of a chip having at least one voltage island and at least one performance screen ring oscillator (PSRO). An on-chip performance monitor (OCPM) is incorporated on the voltage island. Performance measurements of the voltage island are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) are generated with only the voltage island under power. Performance measurements of the performance screen ring oscillator (PSRO) is compared to the performance measurements of the on-chip performance monitor (OCPM) to determine a systematic offset due to the voltage island. Performance models are adjusted using the systematic offset due to the voltage island. | 2009-12-03 |
20090295403 | INTER-DEVICE CONNECTION TEST CIRCUIT GENERATING METHOD, GENERATION APPARATUS, AND ITS STORAGE MEDIUM - A test circuit can use a simple test pattern data without customization for each substrate and considerably reduce a test preparation process. A connection test circuit is generated by receiving the input of the data of the connection relation indicating the devices mutually line-connected among a plurality of devices, the number of connection lines corresponding to the respective connection relations, and the device outputting a test result, sequentially searching for a connection destination device from the output terminal of an output device, and embedding a test circuit module in a test route. | 2009-12-03 |
20090295404 | Test apparatus and test module - Provided is a test apparatus that tests a device under test, comprising a control apparatus that controls the test apparatus; a pattern generator that generates a plurality of test patterns to be provided to a plurality of input terminals of the device under test; a plurality of variable delay circuits that designate a timing for supplying each of the plurality of test patterns to a corresponding input terminal of the plurality of input terminals; and a plurality of micro-controllers that operate in parallel, according to instructions from the control apparatus, to each measure a delay amount of a variable delay circuit when the variable delay circuit is set with a prescribed delay setting value and store the delay setting value in association with the measured delay amount. | 2009-12-03 |
20090295405 | RESONANCE SCANNING SYSTEM AND METHOD FOR TESTING EQUIPMENT FOR ELECTROMAGNETIC RESONANCES - A resonance scanning system and method for testing equipment for electromagnetic resonances uses a resonance detection subsystem with at least one probe to identify at least one of a resonating location, a resonating frequency and a quality factor of a resonance of the equipment and an automatic scanning subsystem to displace the probe to different testing locations of the equipment so that the resonance detection subsystem can determine if any of the different testing locations of the equipment exhibits electromagnetic resonances. | 2009-12-03 |
20090295406 | SILICON MEMS RESONATORS - The invention relates to MEMS resonators. In one embodiment, an integrated resonator and sensor device comprises a micro-electromechanical system (MEMS) resonator, and an anchor portion coupled to the MEMS resonator and configured to allow resonance of the MEMS resonator in a first plane of motion and movement of the MEMS resonator in a second plane of motion. In other embodiments, additional apparatuses, devices, systems and methods are disclosed. | 2009-12-03 |
20090295407 | DEVICE AND HANDLING SYSTEM FOR MEASUREMENT OF MOBILITY AND SHEET CHARGE DENSITY - An apparatus ( | 2009-12-03 |
20090295408 | NANOSTRUCTURED SURFACE FOR MICROPARTICLE ANALYSIS AND MANIPULATION - The present invention provides an apparatus, comprising a first mechanical structure having a first rigid surface, an area of the first rigid surface having a nanostructured surface. The apparatus also includes a second mechanical structure having a second rigid surface and opposing the first mechanical structure. The second rigid surface is cooperable with the nanostructured surface such that a microscopic particle is locatable between the nanostructured surface and the second rigid surface. | 2009-12-03 |
20090295409 | CAPACITIVE VOLTAGE DIVIDER TOUCH SENSOR - A system for measuring capacitance has a measurement circuit with a first reference capacitor connected to a first node and to a second node. Each of the nodes is connected to a unit operable to apply a reference voltage or ground to one of the nodes. Each node has a first pad connected to the first node and a unit operable to measure voltage between the first node and second node. | 2009-12-03 |
20090295410 | OPENING AND CLOSING APPARATUS AND METHOD FOR MANUFACTURING SENSOR SUPPORTING MEMBER - An opening and closing apparatus is disclosed. The opening and closing apparatus includes an opening and closing body, a capacitance sensor, and a sensor support member. The capacitance sensor has a conductive sensor electrode, and outputs a detection signal that corresponds to the capacitance between the sensor electrode and a conductive object located close to the sensor electrode. The sensor support member includes a guard electrode, a holding portion, an attaching portion, and a conductive reinforcing member. The reinforcing member is embedded in the main body. At least a part of the reinforcing member is embedded in the guard electrode such that the reinforcing member is integrated with the guard electrode. | 2009-12-03 |
20090295411 | Occupant Detection System and Method for Calibrating - A method includes measuring a first frequency response of an electrode at a first frequency across a range of environmental conditions, measuring a second frequency response of the electrode at a second frequency across the range of environmental conditions, and comparing the first and second frequency responses measured to define a data set representing an effect of the environmental conditions. An occupant detection system includes an electrode and a detector circuit. The detector circuit is configured to measure an actual frequency response of the electrode and compare the actual frequency response to the data set to determine the effect of the current environmental condition. | 2009-12-03 |
20090295412 | Occupant Detector with Electronic Interference Compensation - A occupant detection system includes an electronic device in communication with a sensor. The system detects an occupant by way of measuring an impedance of an electric field emitted by the sensor. The electronic device is configured to acquire data values from an output signal of the sensor, and reduce the effect of transient electrical interference on the acquired data values and adapt for sustained electrical interference on the acquired data values. A method includes acquiring a new data value, determining whether the new data value represents transient interference, and capturing the new data value if the new data value is free of transient interference and rejecting the new data value if the new data value represents transient interference. | 2009-12-03 |
20090295413 | Sensor System - A sensor system having a sensor unit for detecting a measured variable, and an evaluation unit, which are interconnected via at least one or a plurality of connection line(s), the sensor unit having a sensor, which is connected to a supply voltage, and includes a signal output for a measuring signal that is a function of the measured variable, the evaluation unit having a voltage meter to detect the status of the measured variable as a function of a potential, the sensor unit including a first resistive circuits connected to the sensor, and the evaluation unit including a second resistive circuit connected to the voltage meter. The first and the second resistive circuits are coupled to one another via at least the sensor line and forming a resistor network. The first and the second resistive circuit are configured so that, in a fault-free state of the one or the plurality of connection line(s), the voltage meter detects one or a plurality of measuring potential(s) in one or a plurality of defined measuring potential range(s) as a function of the measured variable, and, in a fault case, it detects a measuring potential that lies within a fault potential range. The first and the second resistive circuits are dimensioned so that the fault potential range lies outside of the one or the plurality of defined measuring potential range(s). | 2009-12-03 |
20090295414 | TRANSIENT EMISSION SCANNING MICROSCOPY - An apparatus for analyzing an integrated circuit to which one or more test signals are applied. An example apparatus includes an objective lens that views reflections from the integrated circuit, a device that houses at least two optical fibers, a component that receives reflections from the objective lens and directs the received reflections to the device, and a photo-diode that receives a reflection received by the device. The apparatus includes a beam splitter that directs reflections from the integrated circuit to a detector. A processing device generates an image signal based on a signal received from the detector and a display outputs an image based on the image signal. The component includes a scan mirror that reflects the collimated reflections to a collimating lens that focuses the reflections from the scan mirror toward the device. | 2009-12-03 |
20090295415 | TESTING OF MULTIPLE INTEGRATED CIRCUITS - A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits. | 2009-12-03 |
20090295416 | REPLACEABLE PROBE APPARATUS FOR PROBING SEMICONDUCTOR WAFER - A probe apparatus for probing a device on a semiconductor wafer to be tested by a testing equipment is provided. The probe apparatus includes a replaceable probe tile removably mounted in a probing location on a base plate. The probe tile is configured into a self-contained assembly which includes a chassis body containing a plurality of probes for probing devices on a wafer, a dielectric block for supporting the probes, and a wireguide for guiding a plurality of cables from the testing equipment into the chassis body. A wafer station having replaceable base plates and replaceable probe tiles are also provided. | 2009-12-03 |
20090295417 | TEST SYSTEM, ELECTRONIC DEVICE, AND TEST APPARATUS - Provided is a test system that tests a device under test, including a plurality of internal test circuits that are provided inside the device under test and that are used for testing an operation circuit of the device under test; a device control section that is electrically connected to the plurality of internal test circuits via a common bus and that controls the plurality of internal test circuits by supplying the common bus with an intra-device control signal corresponding to a received external signal; and a test apparatus that supplies the device control section with the external signal. | 2009-12-03 |
20090295418 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, including a first pipeline that sequentially propagates pieces of pattern data included in a first test pattern, according to a first test period, and outputs the resulting data to the device under test; a second pipeline that sequentially propagates pieces of pattern data included in a second test pattern, according to a second test period that is different from the first test period, and outputs the resulting data to the device under test; a timing control section that controls at least one of a timing at which the first pipeline begins propagating a predetermined first pattern data and a timing at which the second pipeline begins propagating a predetermined second pattern data, based on the first test period and the second test period; and a judging section that judges pass/fail of the device under test based on a signal output by the device under test. | 2009-12-03 |
20090295419 | MEMORY CHIP AND METHOD FOR OPERATING THE SAME - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 2009-12-03 |
20090295420 | SEMICONDUCTOR DEVICE AND TESTING METHOD - A semiconductor device, comprising: a wafer; a radio receiving circuit chip that is formed on the wafer, and receives electric power and a test start signal transmitted by radio from outside; and a plurality of non-volatile memory chips that are formed on the wafer and respectively have self-diagnosis test circuits mounted thereon, wherein, in a test in a wafer state, in response to supply of the electric power and the test start signal from the radio receiving circuit chip through an interchip interconnection, all of the non-volatile memory chips on the wafer simultaneously execute tests by the self-diagnosis test circuits, and respectively write results of the tests into their own memory areas. | 2009-12-03 |
20090295421 | TEST PATTERN OF SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF TESTING DEVICE USING TEST PATTERN - Disclosed are a test pattern of a semiconductor device, a method of manufacturing the same, and a method of testing the device using the test pattern. The test pattern includes a lower metal pattern part formed over a semiconductor substrate, an intermetal insulating film formed over the lower metal pattern part, and upper metal pattern test parts formed over the intermetal insulating film such that the upper metal pattern parts are separated from each other by a designated distance. | 2009-12-03 |
20090295422 | COMPENSATION SCHEME FOR MULTI-COLOR ELECTROLUMINESCENT DISPLAY - A method of compensating for changes in the characteristics of transistors and electroluminescent devices in an electroluminescent display, includes: providing an electroluminescent display having a two-dimensional array of subpixels arranged forming each pixel having at least three subpixels of different colors, with each having an electroluminescent device and a drive transistor, wherein each electroluminescent device is driven by the corresponding drive transistor; providing in each pixel a readout circuit for one of the subpixels of a specific color having a first readout transistor and a second readout transistor connected in series; using the readout circuit to derive a correction signal based on the characteristics of at least one of the transistors in the specific color subpixel, or the electroluminescent device in the specific color subpixel, or both; and using the correction signal to adjust the drive signals. | 2009-12-03 |
20090295423 | COMPENSATION SCHEME FOR MULTI-COLOR ELECTROLUMINESCENT DISPLAY - A method of determining characteristics of transistors and electroluminescent devices, includes: providing an electroluminescent display; providing for pairs of electroluminescent devices drive circuits and a single readout line, each drive circuit including a readout transistor electrically connected to the readout line; providing a first voltage source; providing a second voltage source; providing a current source; providing a current sink; providing a test voltage source; providing a voltage measurement circuit; sequentially testing the drive transistors to provide a first signal representative of characteristics of the drive transistor of the first drive circuit and a second signal representative of characteristics of the drive transistor of the second drive circuit, whereby the characteristics of each drive transistor are determined; and simultaneously testing the first and second electroluminescent devices to provide a third signal representative of characteristics of the pair of electroluminescent devices, whereby the characteristics of both electroluminescent devices are determined. | 2009-12-03 |
20090295424 | Test circuit and method for an electronic device - A test circuit for an electronic device including a liquid crystal display (LCD) device. The LCD device includes a pulse width modulator (PWM) to provide voltages to a display panel of the LCD device, a plurality of feedback circuits to output feedback voltages to the PWM, and a power supply to provide an operating voltage for the PWM. When the electronic device is in a test mode, the feedback circuits respectively decrease the feedback voltages, such that the PWM increases the voltages output to the display panel according to the feedback voltages, the increased voltages reach predetermined test voltages and test the electronic device. | 2009-12-03 |
20090295425 | DIRECT DETECT SENSOR FOR FLAT PANEL DISPLAYS - Each sensor of a linear array of sensors includes, in part, a sensing electrode and an associated feedback circuit. The sensing electrodes are adapted to be brought in proximity to a flat panel having formed thereon a multitude of pixel electrodes in order to capacitively measure the voltage of the pixel electrodes. Each feedback circuit is adapted to actively drive its associated electrode via a feedback signal so as to maintain the voltage of its associated electrode at a substantially fixed bias. Each feedback circuit may include an amplifier having a first input terminal coupled to the sensing electrode and a second input terminal coupled to receive a biasing voltage. The output signal of the amplification circuit is used to generate the feedback signal that actively drives the sensing electrode. The biasing voltage may be the ground potential. | 2009-12-03 |
20090295426 | DYNAMICALLY ADJUSTING OPERATION OF A CIRCUIT WITHIN A SEMICONDUCTOR DEVICE - Apparatus including a reference circuit configured to provide a particular impedance and having a first plurality of switching devices and a resistive device coupled to each other in parallel; a second plurality of switching devices coupled to each other in parallel and coupled in series with the reference circuit between a supply node and a supply return node; and processing logic coupled to the second plurality of switching devices and configured to selectively enable and disable a combination of switching devices of the second plurality of switching devices that results in an impedance of the enabled switching devices more closely matching the particular impedance of the reference circuit than at least one other combination of enabled and disabled switching devices of the second plurality of switching devices. | 2009-12-03 |
20090295427 | Programmable switch circuit and method, method of manufacture, and devices and systems including the same - A switching circuit can include a logic circuit having a logic circuit input and a logic circuit output and at least three input transistors coupled to provide three separate paths between three input/output (I/O) nodes and the logic circuit input. The switching circuit can further include at least three output transistors coupled to provide three separate paths between the three I/O nodes and the logic circuit output. Methods of fabricating such switch circuits and devices and/or systems including such switching circuits are also disclosed. | 2009-12-03 |
20090295428 | THREE-VALUED LOGIC FUNCTION CIRCUIT - There is provided a three-valued logic function circuit capable of remarkably reducing the kinds of basic circuits necessary for realizing all 3 | 2009-12-03 |
20090295429 | BIDIRECTIONAL BUFFER CIRCUIT AND SIGNAL LEVEL CONVERSION CIRCUIT - A bidirectional buffer circuit includes a first terminal, a second terminal, a first output buffer to which a signal from the first terminal is input and which outputs the signal to the second terminal, a first one-shot buffer control circuit outputting a first control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, a first one-shot buffer temporarily driving the second terminal by the first control signal, a second output buffer to which a signal from the second terminal is input and which outputs the signal to the first terminal, a second one-shot buffer control circuit outputting a second control signal according to an earlier arriving signal out of a signal from the first terminal and a signal from the second terminal, and a second one-shot buffer temporarily driving the first terminal by the second control signal. | 2009-12-03 |
20090295430 | METHOD AND APPARATUS FOR SIMULTANEOUS PROCESSING OF MULTIPLE FUNCTIONS - A methodology for describing an input-output behavior of a multi-level logic gate to process simultaneously a multiplicity of independent Boolean logic functions, with each Boolean function processing signals carried on an individual, separate channel. An embodiment may simultaneously process the same data with the same function or with different functions, multiple data with the same function, or multiple data with different functions. In addition, multi-level logic signals (having more than two levels) may be processed, so that a higher communication bandwidth may be obtained without necessarily increasing the number of traces (wires). Other embodiments are described and claimed. | 2009-12-03 |
20090295431 | INTEGRATED NANOTUBE AND FIELD EFFECT SWITCHING DEVICES - Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit. | 2009-12-03 |
20090295432 | CMOS BACK-GATED KEEPER TECHNIQUE - A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (V | 2009-12-03 |
20090295433 | METHOD AND APPARATUS FOR MEASURING AND COMPENSATING FOR STATIC PHASE ERROR IN PHASE LOCKED LOOPS - A method and circuit for static phase error measurement includes a reference clock delay chain having a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a reference clock signal. A feedback signal delay chain also has a selectable number of delay elements. A number of the delay elements are enabled in accordance with a select length signal to delay a feedback signal. A latch tests phase alignment between the delayed reference clock signal and the delayed feedback signal and outputs a measurement of static phase error. | 2009-12-03 |
20090295434 | SIGNAL RECEIVING DEVICE - A signal receiving device includes: a first conversion unit comprising a first input terminal to which a signal including a voltage signal and a reference voltage is inputted, and a first output terminal which output a first current signal voltage-current converted from the signal; a second conversion unit comprising a second input terminal to which the reference voltage is inputted, and a second output terminal which output a second current signal voltage-current converted from the reference voltage; a current mirror circuit comprising a third input terminal to which the second current signal is inputted, and a third output terminal which output a third current signal corresponding to the second current signal; and an output unit connected to both the first and third output terminals. | 2009-12-03 |
20090295435 | METHOD AND APPARATUS FOR REDUCING SPURS IN A FRACTIONAL-N SYNTHESIZER - A method and apparatus for reducing in-band spurs in a fractional-N synthesizer ( | 2009-12-03 |
20090295436 | ELECTRONIC CIRCUIT, FREQUENCY DIVIDER AND RADIO SET - A master stage | 2009-12-03 |
20090295437 | SIGNAL WAVEFORM GENERATING CIRCUIT AND METHOD - A signal waveform generating circuit includes a first part storing waveform data of a signal to be generated, a second part storing additional data for adjusting the waveform data, and a third part adjusting the waveform data read from the first part by the additional data read from the second part. | 2009-12-03 |
20090295438 | Optimum Timing of Write and Read Clock Paths - An apparatus and method for timing calibration of write and read-back data exchanges between respective dies of an external memory/external device has a master arbiter or, alternatively, a test mux between a system bus master interface and an external memory controller for driving the external memory/external device, a calibration circuit under control of the master arbiter via a test bus master interface to provide stepped-through time delays for test data exchanges between the dies, and the calibration circuit obtains pass/fail data indicating pass or fail of the varied time delays for the test data exchanges. A processor system at the system bus master interface selects calibration values corresponding to pass data, and applies the calibration values to the respective dies for timing of write and read-back data exchanges between the dies. | 2009-12-03 |
20090295439 | Phase Lock Loop (PLL) with Gain Control - A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision. | 2009-12-03 |
20090295440 | Systems and Methods for Cancelling Phase-Locked Loop Supply Noise - One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise. | 2009-12-03 |
20090295441 | APPARATUS AND METHOD FOR MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount. | 2009-12-03 |
20090295442 | APPARATUS AND METHOD FOR MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a clock divider generating first and second intermediate signals having edges delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay element delaying the first intermediate signal by a first delay amount; a second delay element delaying the first intermediate signal by a second delay amount; a third delay element delaying the second intermediate signal by a third delay amount; and a fourth delay element delaying the second intermediate signal by a fourth delay amount. The third delay amount is equal to the first delay amount. The fourth delay amount is equal to the second delay amount. The apparatus also includes a delay detection loop to adjust the second and fourth delays. | 2009-12-03 |
20090295443 | System and Method For Modifying Signal Characteristics - The present invention embodiments provide a system to modify signal characteristics to produce a desired signal. The system comprises a signal module to modify signal characteristics. The signal module includes at least one input to receive an input signal including a substantially rectangular signal and one or more control signals and an output to provide a substantially trapezoidal signal. A signal unit of the signal module adjusts characteristics of the substantially rectangular signal including leading and/or trailing edges of that signal in accordance with the one or more control signals to produce the substantially trapezoidal signal. The present invention embodiments further include a probe card and method to adjust signal characteristics as described above. | 2009-12-03 |
20090295444 | PHASE RECOVERY CIRCUIT - A phase recovery circuit for avoiding noise interfering with the clock signal generated from an oscillator is disclosed. The phase recovery circuit includes a noise detector, a phase detector, and a phase locker. The noise detector detects noise and accordingly generates a noise detecting signal. The phase detector is triggered by the noise detecting signal for detecting the phase of the clock signal and accordingly generating a phase detecting signal. The phase locker locks the phase of the clock signal to a predetermined phase within a predetermined period after the occurrence of the noise detecting signal, and after the predetermined period, the phase locker releases the clock signal. In this way, the phase of the clock signal is not affected by noise. | 2009-12-03 |
20090295445 | DOUBLE-EDGE PWM CONTROLLER AND ITS CONTROL METHOD THEREOF - The present invention discloses a double-edge pulse width modulation (PWM) controller based on the output current and output voltage which is modulated in real time by the output current and the output voltage. The controller uses an extra first adder to sum up the compensation signal and a triangular signal (or a saw-tooth signal); a second adder to sum up the output current signal to a bias value; a PWM comparator, with its non-inverting input receiving the output of said first adder, its inverting input receiving the output of said second adder and outputs the PWM signal. | 2009-12-03 |
20090295446 | DUTY CYCLE CORRECTING CIRCUIT AND METHOD OF CORRECTING A DUTY CYCLE - A duty cycle correcting circuit includes a duty ratio control unit configured to alternately change logical values of a plurality of bits of a pull-up control signal and a plurality of bits of a pull-down control signal in response to a duty ratio detection signal, a duty ratio correcting unit configured to adjust driving abilities of a first driver and a second driver in response to the plurality of bits of the pull-up control signal and the plurality of bits of the pull-down control signal to output a correction clock signal, and a duty ratio detecting unit configured to detect a duty ratio of the correction clock to generate the duty ratio detection signal. | 2009-12-03 |
20090295447 | APPARATUS AND METHODS FOR A HIGH-VOLTAGE LATCH - Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described. | 2009-12-03 |
20090295448 | Radiation Hardened CMOS Master Latch With Redundant Clock Input Circuits and Design Structure Therefor - A radiation hardened master latch for use in a programmable phase frequency divider operating at GHz frequencies is implemented in deep submicron CMOS technology, and consists of two identical half circuits interconnected in a DICE-type configuration that makes the master latch immune to a single event upset (SEU) affecting at most one of its four data inputs. Each half circuit includes a clock input circuit with four sub-clock nodes each coupled by an inverter to a common clock input. The clock input circuit is configured to be redundant, such that the operation of the master latch half circuit is also immune to an SEU affecting at most one the inverters associated with the plurality of sub-clock nodes. The radiation hardened master latch resides in a design structure embodied in a machine readable medium storing information for designing, manufacturing and/or testing the master latch. | 2009-12-03 |
20090295449 | DUTY CYCLE MEASUREMENT CIRCUIT FOR MEASURING AND MAINTAINING BALANCED CLOCK DUTY CYCLE - A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance. | 2009-12-03 |
20090295450 | Signal Processing Apparatus, Signal Processing System and Signal Processing Method - A signal processing apparatus is provided, which generates a data signal having a signal waveform corresponding to a first bit value of a signal waveform transitioning from a high level to a low level or a signal waveform transitioning from a low level to a high level, a pre-transition signal level corresponding to a second bit value of one of a plurality of high levels and a plurality of low levels, and a post-transition signal level corresponding to a third bit value of the other. | 2009-12-03 |
20090295451 | Systems and Methods of Digital Isolation with AC/DC Channel Merging - Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal. | 2009-12-03 |
20090295452 | BOOSTING CIRCUIT - A boosting circuit configuration with high boosting efficiency is provided which is based on a boosting circuit that performs an operation in accordance with a two-phase clock and which includes a plurality (M≧4) of boosting cell sequences (units). A boosting cell in a K-th sequence (1≦K≦M) is controlled, depending on the potential of the output terminal of a boosting cell in a KA-th sequence (KA=(K−1) when (K−1)>0, and KA=M when (K−1)=0). Thereby, before a clock input to the boosting cell in the K-th sequence goes from “L” to “H”, so that boosting is performed, a charge transfer transistor can be caused to go from the conductive state to the non-conductive state, so that a backflow of charges via charge transfer transistor can be prevented. | 2009-12-03 |
20090295453 | SIGNAL READING METHOD, SIGNAL READING CIRCUIT, AND IMAGE SENSOR - A signal reading method successively outputs a read signal by scanning a voltage value of an integrating capacitor in an image sensor in which a plurality of sensor parts are arranged in a two-dimensional array made up of rows and columns and each sensor part includes the integrating capacitor accumulating a charge obtained by integrating a photocurrent output from a sensor. A first integration of the photocurrent using the integrating capacitor and a first sampling and holding using a sample and hold capacitor are performed in a first time interval, during a time of one frame made up of the first through third time intervals. A second integration of the photocurrent using the integrating capacitor is performed in the second time interval, and processes in the first and second time intervals are performed in common with respect to all of the sensor parts simultaneously. A vertical scan is started by selecting the row in an order starting from a first row. | 2009-12-03 |
20090295454 | LOW VOLTAGE MIXER CIRCUIT - A mixer circuit ( | 2009-12-03 |
20090295455 | SYSTEM FOR CONTROLLING AN ELECTRONIC DRIVER FOR A NEBULISER - A system for controlling an electronic driver for a nebuliser or aerosol, the system comprising: an H-bridge driver for connection around a membrane to be driven; a voltage source for applying a voltage to the H-bridge driver; a feedback loop from the H-bridge to a phase shift oscillator, the output of which enters the H-bridge driver; wherein the H-bridge driver includes at least one sense resistor for detecting the phase angle between the applied voltage to the H-bridge driver and the applied current. | 2009-12-03 |
20090295456 | SWITCHING CIRCUIT AND IMAGING APPARATUS UTILIZING THE SAME - In a complementary-MOSFET driving circuit for driving the charge multiplication gate of an EM-CCD, a ferrite bead is connected to a conduction-termination direction diode in parallel thereto, the conduction-termination direction diode being inserted into the gate electrodes of complementary MOSFETs in series therewith, the impedance of the ferrite bead at a switching frequency being lower than one-half of the gate-electrode impedance of the MOSFETs, a time during which the MOSFETs are brought into simultaneous conduction being shorter than ¼th of the switching period, the impedance of the ferrite bead at a frequency equivalent to ¼th of the switching period being higher than 2 times the gate-electrode impedance of the MOSFETs, a ferrite bead being connected to the drain electrodes of the complementary MOSFETs in series therewith, the impedance of the ferrite bead at the switching frequency being lower than one-half of the impedance of a capacitive load at the switching frequency, and the impedance of the ferrite bead, at a frequency equivalent to ¼th of the switching period being higher than 2 times the impedance of the capacitive load. | 2009-12-03 |
20090295457 | COLD TEMPERATURE CONTROL IN A SEMICONDUCTOR DEVICE - Operation of complex integrated circuits at low temperatures may be enhanced by providing active heating elements within the integrated circuit so as to raise the temperature of at least critical circuit portions at respective operational phases, such as upon power-up. Consequently, enhanced cold temperature performance may be obtained on the basis of existing process elements in order to provide design stability without requiring extensive circuit simulation or redesign of well-established circuit architectures. | 2009-12-03 |
20090295458 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD FOR THE SAME - The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit. | 2009-12-03 |
20090295459 | Temperature control device - A temperature control device for controlling temperature of semiconductor device. The temperature control device comprising, a leak current detection unit for detecting leak current of the semiconductor device, and a temperature control unit for controlling temperature of the semiconductor device so that the leak current is within predetermined current range, if the leak current exceed the predetermined current range. | 2009-12-03 |
20090295460 | ELECTRONIC DEVICE AND METHOD FOR EVALUATING A VARIABLE CAPACITANCE - An apparatus is provided. The apparatus comprises a digital signal generator, an analog filter, an amplitude modulator, and an analog-to-digital converter (ADC). The digital signal generator has a demodulator and provides a digital excitation signal. The analog filter is coupled to the digital signal generator. The amplitude modulator has a variable capacitor and is coupled to the analog filter. The amplitude modulator also generates an amplitude modulated signal with an amplitude that is a function of the capacitance of the variable capacitor. The ADC is coupled to the amplitude modulator and the demodulator, and the digital signal generator and the demodulator operate synchronously. | 2009-12-03 |
20090295461 | DEVICE CONFIGURATION - A process and apparatus for configuring one or more integrated circuits within a device in a manufacturing process is described. In an exemplary process, a device is manufactured by assembling a chip onto a board such as a printed circuit substrate and the chip is fused from power routed across the board to the chip. The power source for the fusing can be generated from the internal power supply on the board or received on a test point on the board itself or a connection interface (e.g. a USB interface) coupled to the board. In an exemplary apparatus, a device comprises a chip with a plurality of fuses that are used to configure the device and a board coupled to the chip, with the board capable of routing power from the board to the chip and the power is used to blow one or more of the plurality of fuses. | 2009-12-03 |
20090295462 | Voltage Divider, Constant Voltage Circuit Using Same, And Trimming Method In The Voltage Divider Circuit - A voltage divider circuit generating a divided voltage by dividing an input voltage with a predetermined voltage division ratio, and outputting the divided voltage is disclosed. The voltage divider circuit includes a first resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses; and a second resistor circuit including multiple resistors connected in series, the resistors being connected in parallel to corresponding fuses, the second resistor circuit being connected in series to the first resistor circuit. The divided voltage is output from the connection of the first resistor circuit and the second resistor circuit, and the fuses of the first resistor circuit and the second resistor circuit are subjected to trimming so that the combined resistance of the first resistor circuit and the second resistor circuit is constant. | 2009-12-03 |
20090295463 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a first lower-layer line for supplying power to a transistor formed on the semiconductor substrate, a first interlayer line which is connected to the first lower-layer line, and an allowable current of which is larger than that of the first lower-layer line; and an upper-layer line which is provided above the first interlayer line and receives power input from outside. The first interlayer line is connected to the upper-layer line through a switch circuit formed on the semiconductor substrate. | 2009-12-03 |
20090295464 | BOOSTER CIRCUIT - Analog comparison circuits are provided, each of which compares the potentials of the same stage of a first boosting cell row and a second boosting cell row and selecting and outputting the lower potential. The P-well potentials of switching devices having a triple-well structure are controlled using the output potentials of these analog comparison circuits. As a result, the amplitude of the P-well potential can be suppressed and a common P-well region can be arranged. | 2009-12-03 |
20090295465 | ALL NPN-TRANSISTOR PTAT CURRENT SOURCE - The present invention relates to an improved PTAT current source and a respective method for generating a PTAT current. Opportune collector currents are generated and forced in two transistors exploiting the logarithmic relation between the base-emitter voltage and the collector current of a transistor. A resistor senses a voltage difference between the base-emitter voltages of the two transistors, which can have either the same or different areas. A fraction of the current flowing through the resistor is forced into a transistor collector and mirrored by an output transistor for providing an output current. By this principle an all npn-transistor PTAT current source can be provided that does not need pup transistors as in conventional PTAT current sources. The invention is generally applicable to a variety of different types of integrated circuits needing a PTAT current reference, especially in modern advanced technologies as InP and GaAs where p-type devices are not available. For example, the PTAT current source circuit of the invention can be used in radio frequency power amplifiers, in radio frequency tag circuits, in a satellite microwave front-end. | 2009-12-03 |
20090295466 | METHOD TO REDUCE VARIATION IN CMOS DELAY - Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced. | 2009-12-03 |
20090295467 | CIRCUITRY AND METHOD FOR BUFFERING A POWER MODE CONTROL SIGNAL - A circuit has an input for receiving a power mode control signal to indicate a low power mode. A plurality of non-inverting buffers forms a fanout signal distribution network and provides buffering of the power mode control signal for gated power domain functional circuitry. Each non-inverting buffer has an even number of serially-connected inverting gates, at least a portion providing respective outputs having a valid logic state in the low power mode. Two voltages are used, one of which is disconnected during the low power mode. The non-inverting buffers have a first inverting gate connected to a continuous voltage terminal and a second inverting gate, collectively sized larger than the first inverting gate and connected to a voltage terminal which is selectively disconnected during the low power mode from the continuous voltage terminal. | 2009-12-03 |
20090295468 | System for minimizing the power consumption of a device in a power down mode - A system is disclosed for reducing power drain of a component when the component is in a powered down state. The system comprises a power input configured to receive power, a power output to the component, monitor logic configured to monitor a level of power moving between the input and output, and control logic configured to control power transfer between the input and output. The control logic may be in communication with the monitor logic and configured to selectively restrict power flow between the input and output when the monitor logic senses that power flow between the input and output falls below a threshold level. A method comprises checking a power level between the input and output, and if the power level exceeds a threshold, then permitting substantially unrestricted power flow. If the power level is less than the threshold, then restricting the power level between the input and output. | 2009-12-03 |
20090295469 | PRIMARY SIDE CONTROL CIRCUIT AND METHOD FOR ULTRA-LOW IDLE POWER OPERATION - A method and circuit for reducing power consumption during idle mode to ultra-low levels, such as about 1/10 | 2009-12-03 |
20090295470 | FAST TURN ON ACTIVE DCAP CELL - A fast active DCAP cell which has a short turn-on time, achieves a high capacitance density, and which minimizes leakage overhead during its normal operation mode is disclosed. The DCAP cell has a pair of PMOS transistors that have their drains connected to a gate of a PMOS transistor and their sources connected to the VDD rail. The drain and source of the PMOS transistor are connected to the VSS rail. Likewise, the DCAP cell has a pair of NMOS transistors that have their drains connected to a gate of an PMOS transistor and their sources connected to the VSS rail. The drain and source of the PMOS transistor are connected to the VDD rail. None of the gates of the transistors is connected to the VDD or VSS rail. This protects the gate oxide from being damaged by ESD surge currents. | 2009-12-03 |