52nd week of 2011 patent applcation highlights part 44 |
Patent application number | Title | Published |
20110318883 | POWER SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF - A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided. | 2011-12-29 |
20110318884 | PRODUCTION METHOD OF SEMICONDUCTOR MODULE WITH RESIN-MOLDED ASSEMBLY OF HEAT SPREADER AND SEMICONDUCTOR CHIP - A method of producing a semiconductor module which includes a resin molded package and a coolant passage is provided. The resin molded package is made up of a thermosetting resin-made mold and a thermoplastic resin-made mold. The resin molded package is formed by making the thermoplastic resin-made mold, placing the thermoplastic resin-made mold and a semiconductor sub-assembly made up of a power semiconductor chip, heat spreaders, terminals, etc., and then forming the thermosetting resin-made mold. Specifically, the thermosetting resin-made mold is made after the thermoplastic resin-made mold, thereby creating a high degree of adhesion of the thermosetting resin-made mold to the thermoplastic resin-made mold before the thermosetting resin-made mold is hardened completely, thereby forming firmly an adhered interface between the thermosetting resin-made mold and the thermoplastic resin-made mold. This minimizes the risk of occurrence of air gaps at the adhered interface and avoids the leakage of the coolant outside the resin molded package. | 2011-12-29 |
20110318885 | Thermally and Electrically Enhanced Ball Grid Array Package - In one embodiment, a method for assembling a ball grid array (BGA) package is provided. The method includes providing a stiffener that has opposing first and second surfaces, wherein the first surface is capable of mounting an integrated circuit (IC) die in a central area and forming a pattern in at least a portion of the first surface to enhance the adhesiveness of an encapsulant material to the first surface. | 2011-12-29 |
20110318886 | METHOD FOR FORMING CIRCUIT PATTERNS ON SURFACE OF SUBSTRATE - A method for forming circuit patterns on a surface of a substrate is provided and has steps of: providing and pre-heating a substrate having an insulation surface on one side thereof; providing an activation connection device for oscillating and painting an activation solder onto the pre-heated insulation surface to heat and melt the activation solder; applying ultrasonic waves to the melted activation solder by the activation connection device, so as to activate the activation solder and the insulation surface by the ultrasonic waves; and moving the activation connection device, so as to form a circuit pattern on the insulation surface by the activation solder. | 2011-12-29 |
20110318887 | METHOD OF MOLDING SEMICONDUCTOR PACKAGE - A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding. | 2011-12-29 |
20110318888 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises the steps of forming a seed over the insulating film by introducing hydrogen and a deposition gas into a first treatment chamber under a first condition and forming a microcrystalline semiconductor film over the seed by introducing hydrogen and the deposition gas into a second treatment chamber under a second condition: a second flow rate of the deposition gas is periodically changed between a first value and a second value; and a second pressure in the second treatment chamber is higher than or equal to 1.0×10 | 2011-12-29 |
20110318889 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device is reduced. Provision of a crack suppression layer formed of a metal film in the periphery of a semiconductor element makes it possible to suppress a crack occurring from the outer periphery of a substrate and reduce damage to the semiconductor element. In addition, even if the semiconductor device is subjected to physical forces from the outer periphery in separation and transposition steps, progression (growth) of a crack to the semiconductor device can be suppressed by the crack suppression layer. | 2011-12-29 |
20110318890 | METHODS OF FORMING SEMICONDUCTOR-ON-INSULATING (SOI) FIELD EFFECT TRANSISTORS WITH BODY CONTACTS - Semiconductor-on-insulator (SOI) field effect transistors include a semiconductor substrate and a first semiconductor active region on a first portion of a surface of the substrate. A first electrically insulating layer is provided. This first electrically insulating layer extends on a second portion of the surface of the substrate and also on a first sidewall of the first semiconductor active region. A second electrically insulating layer is provided, which extends on a third portion of the surface of the semiconductor substrate. The second electrically insulating layer also extends on a second sidewall of the first semiconductor active region. A second semiconductor active region is provided on the first semiconductor active region. The second semiconductor active region extends on the first semiconductor active region and on ends of the first and second electrically insulating layers. Source and drain regions are also provided, which are electrically coupled to opposite ends of the second semiconductor active region. An insulated gate electrode extends on the second semiconductor active region and opposite the first semiconductor active region. | 2011-12-29 |
20110318891 | METHOD OF CRYSTALLIZING SILICON THIN FILM AND METHOD OF MANUFACTURING SILICON THIN-FILM TRANSISTOR DEVICE - A method of crystallizing a silicon thin film, which enables uniforming the size of a crystalline grain of the silicon thin film, includes: a second process of stacking, on a substrate, a first gate electrode having a first reflectivity; a third process of stacking a second gate electrode on the first gate electrode, the second gate electrode having a second reflectivity lower than the first reflectivity and including a top face having an area smaller than an area of the top face of the first gate electrode; a fourth process of stacking a gate insulation film to cover a first region and a second region; a fifth process of stacking a noncrystalline silicon thin film on the stacked gate insulation film; and a sixth process of crystallizing the noncrystalline silicon thin film by irradiating the noncrystalline silicon thin film from above with a laser beam. | 2011-12-29 |
20110318892 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a source electrode and a drain electrode formed over a semiconductor substrate, a gate electrode formed over the semiconductor substrate and disposed between the source electrode and the drain electrode, a protection film made of an insulating material and formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode, and a gate side opening formed at least in one of a portion of the protection film-between the source electrode and the gate electrode and a portion of the protection film between the drain electrode and the gate electrode and disposed away from all of the gate electrode, the source electrode and the drain electrode. | 2011-12-29 |
20110318893 | METHODS FOR FORMING SEMICONDUCTOR DEVICE STRUCTURES - The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. | 2011-12-29 |
20110318894 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a first semiconductor region of a second conductivity type on a semiconductor layer of a first conductivity type, forming a mask selectively opening a surface of the first semiconductor region, and forming a trench penetrating through the first semiconductor region to reach the semiconductor layer. The method can include exposing further a part of the surface of the first semiconductor region from the mask. The method can include forming a control electrode in the trench, and forming selectively a second semiconductor region of the first conductivity type on the surface of the first semiconductor region. The method can include removing the mask having the opening. The method can include forming selectively a third conductor region of the second conductivity type on the surface of the first semiconductor region. | 2011-12-29 |
20110318895 | FABRICATION METHOD OF TRENCHED POWER MOSFET - A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench. | 2011-12-29 |
20110318896 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device having a raised source and drain structure, in forming a raised region by etching, etching of an island-like semiconductor film which is an active layer is inhibited. In a method for manufacturing a semiconductor device, an insulating film is formed by oxidizing or nitriding the surface of an island-like semiconductor film, a semiconductor film is formed on a region which is a part of the insulating film, a gate electrode is formed over the insulating film, an impurity element imparting one conductivity type is added to the island-like semiconductor film and the semiconductor film using the gate electrode as a mask, the impurity element is activated by heating the island-like semiconductor film and the semiconductor film, and the part of the insulating film between the island-like semiconductor film and the semiconductor film disappears by heating the island-like semiconductor film and the semiconductor film. | 2011-12-29 |
20110318897 | Method of Forming a Shallow Trench Isolation Embedded Polysilicon Resistor - Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants. | 2011-12-29 |
20110318898 | HARD MASK FOR THIN FILM RESISTOR MANUFACTURE - Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer. | 2011-12-29 |
20110318899 | Methods of Forming Capacitors - Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O | 2011-12-29 |
20110318900 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided. | 2011-12-29 |
20110318901 | SEMICONDUCTOR DEVICE WITH GATE-UNDERCUTTING RECESSED REGION - A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure. | 2011-12-29 |
20110318902 | METHODS OF FABRICATING FLASH MEMORY DEVICES HAVING SHARED SUB ACTIVE REGIONS - Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region. | 2011-12-29 |
20110318903 | MANUFACTURING METHOD FOR FIN-FET HAVING FLOATING BODY - A manufacturing method for a FIN-FET having a floating body is disclosed. The manufacturing method of this invention includes forming openings in a poly crystalline layer; extending the openings downward; forming spacers on sidewalls of the openings; performing an isotropic silicon etching process on bottoms of the openings; performing deposition by using TEOS to form gate oxide. | 2011-12-29 |
20110318904 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided. | 2011-12-29 |
20110318905 | SILICON/GERMANIUM NANOPARTICLE INKS, LASER PYROLYSIS REACTORS FOR THE SYNTHESIS OF NANOPARTICLES AND ASSOCIATED METHODS - Laser pyrolysis reactor designs and corresponding reactant inlet nozzles are described to provide desirable particle quenching that is particularly suitable for the synthesis of elemental silicon particles. In particular, the nozzles can have a design to encourage nucleation and quenching with inert gas based on a significant flow of inert gas surrounding the reactant precursor flow and with a large inert entrainment flow effectively surrounding the reactant precursor and quench gas flows. Improved silicon nanoparticle inks are described that has silicon nanoparticles without any surface modification with organic compounds. The silicon ink properties can be engineered for particular printing applications, such as inkjet printing, gravure printing or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon nanoparticles. | 2011-12-29 |
20110318906 | Separation Apparatus, Separation Method, and Method for Manufacturing Semiconductor Element - Objects are to reduce the number of steps in a process for separating a substrate and a semiconductor element, to provide a separation apparatus capable of reducing the number of steps, to suppress manufacturing cost by reducing the number of steps in a separation process, and to improve productivity in manufacturing semiconductor elements. A separation apparatus including a frame body, a porous body having a chamfered, rounded corner portion, a suction unit configured to create suction in the porous body and the frame body, and a jig which includes a unit adopted to press down part of an object to be separated and a unit adopted to lift another part of the object to be separated, and also a separation method and a method for manufacturing a semiconductor element by using the separation apparatus, are provided. | 2011-12-29 |
20110318907 | COMPOSITION FOR FORMING GATE INSULATING FILM FOR THIN-FILM TRANSISTOR - There is provided a novel composition for forming a gate insulating film taking into consideration also electrical characteristics after other processes such as wiring by irradiation with an ultraviolet ray and the like during the production of an organic transistor using a gate insulating film. A composition for forming a gate insulating film for a thin-film transistor comprising: a component (i): an oligomer compound or a polymer compound containing a repeating unit having a structure in which a nitrogen atom of a triazine-trione ring is bonded to a nitrogen atom of another triazine-trione ring through a hydroxyalkylene group; and a component (ii): a compound having two or more blocked isocyanate groups in one molecule thereof. | 2011-12-29 |
20110318908 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS - The present invention is a semiconductor manufacturing apparatus by which an impurity can be introduced into an active layer at a low and a stable concentration in order to form semiconductor elements that have little variation in threshold voltage. In the semiconductor manufacturing apparatus that includes a washing unit; an impurity introduction unit used to attach the impurity to the surface of the semiconductor film; a laser crystallization unit used to crystallize the semiconductor film to which an impurity has been attached; and transfer robots, the amount of the impurity attached to the semiconductor film is controlled by the length of time of exposure of the substrate in the impurity introduction unit, and the semiconductor film is crystallized while a crystalline semiconductor film that contains an impurity at low concentration is formed simultaneously by laser crystallization. | 2011-12-29 |
20110318909 | SYSTEM AND METHOD OF SEMICONDUCTOR MANUFACTURING WITH ENERGY RECOVERY - The invention can provide or facilitate energy recovery operations during semiconductor processing operations by utilizing a bell jar having a radiation shield thereon that is comprised of a mediating layer comprising nickel disposed on an interior surface of the bell jar, and a reflective layer which can comprise a gold layer that is disposed on the mediating layer. The reflective layer has an emissivity of less than 5% and, more preferably, the reflective layer has an emissivity of less than about 1%. Heat from the reaction chamber can be used to reduce the heating load of one or more other unit operations. | 2011-12-29 |
20110318910 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device that sufficiently activates a deep ion injection layer and fully recovers lattice defects generated in the ion injection process. Laser light pulses are successively emitted to form substantially CW (continuous wave) laser light. This feature of the invention stably performs activation of a deep ion injection layer at about 2 μs with few defects. | 2011-12-29 |
20110318911 | NONVOLATILE MEMORY CELL COMPRISING A REDUCED HEIGHT VERTICAL DIODE - A method for forming a nonvolatile memory cell is provided that includes: (1) forming a rail-shaped first conductor above a substrate, (2) forming a rail-shaped second conductor above the first conductor, and (3) forming a substantially vertical first pillar disposed between the first conductor and the second conductor. The first pillar includes a vertically oriented p-i-n diode, and the p-i-n diode includes: (a) a bottom heavily doped region having a first conductivity type, (b) a middle intrinsic or lightly doped region, and (c) a top heavily doped region having a second conductivity type opposite the first conductivity type. The bottom heavily doped region is doped by implantation of arsenic ions and the top heavily doped region is doped by implantation of BF | 2011-12-29 |
20110318912 | Methods for preparing a semiconductor wafer with high thermal conductivity - This invention generally relates to an epitaxial silicon semiconductor wafer with increased thermal conductivity to transfer heat away from a device layer, while also having resistance to common failure mechanisms, such as latch-up failures and radiation event failures. The semiconductor wafer comprises a lightly-doped device layer, a highly-doped protective layer, and a lightly-doped substrate. The invention is also directed to a process for forming such an epitaxial silicon wafer. | 2011-12-29 |
20110318913 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode. | 2011-12-29 |
20110318914 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device, in which an interference effect between word lines is substantially reduced or eliminated, includes forming a plurality of gate patterns on a substrate; forming a first insulating layer between the gate patterns, the first insulating layer filling a region between the gate patterns; etching the first insulating layer to remove a portion of the first insulating layer to a predetermined depth; and forming a second insulating layer on the gate patterns and the first insulating layer. A low-dielectric-constant material is formed between the gate patterns. | 2011-12-29 |
20110318915 | PROCESS TO MAKE HIGH-K TRANSISTOR DIELECTRICS - A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer. | 2011-12-29 |
20110318916 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer. | 2011-12-29 |
20110318917 | METHODS OF FORMING THROUGH-SILICON VIA STRUCTURES INCLUDING CONDUCTIVE PROTECTIVE LAYERS - Through-Silicon-Via (TSV) structures can be provided by forming a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate, that is opposite the upper surface, and having a conductive protective layer comprising Ni and/or Co formed at a bottom of the conductive via. A polymer insulating layer can be formed on the backside surface that is separate from the substrate and in contact with the conductive protective layer. | 2011-12-29 |
20110318918 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE ALLOWING SMOOTH BUMP SURFACE - A method of fabricating a semiconductor device, includes: removing, after forming solder for forming a plurality of bumps on a semiconductor substrate, an oxide film formed on a surface of the solder while heating the semiconductor substrate with first radiant heat; and heating the semiconductor substrate with an amount of second radiant heat that is greater than the amount of the first radiant heat by holding the semiconductor substrate at a position apart from a front surface of a heater stage at a predetermined distance to reflow the solder from which the oxide film is removed. | 2011-12-29 |
20110318919 | SURFACE TREATMENT FOR A FLUOROCARBON FILM - A method for manufacturing semiconductor devices includes the steps of annealing an insulating layer and forming a barrier layer including a metal element over the insulating layer. The insulating layer includes a fluorocarbon (CFx) film. The barrier layer is formed by a high-temperature sputtering process after the annealing step. | 2011-12-29 |
20110318920 | LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE - A method of annealing semiconductor devices to form substantially ohmic contact regions between a layer of wide band-gap semiconductor material and contact areas disposed thereon includes exposing the semiconductor devices to an annealing temperature less than approximately 900 degrees Celsius for an annealing duration of greater than approximately two hours. | 2011-12-29 |
20110318921 | Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM - The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated. | 2011-12-29 |
20110318922 | METHOD OF FORMING SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 2011-12-29 |
20110318923 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME INCLUDING A CONDUCTIVE STRUCTURE IS FORMED THROUGH AT LEAST ONE DIELECTRIC LAYER AFTER FORMING A VIA STRUCTURE - For forming a semiconductor device, a via structure is formed through at least one dielectric layer and at least a portion of a substrate. In addition, a protective buffer layer is formed onto the via structure. Furthermore, a conductive structure for an integrated circuit is formed over the substrate after forming the via structure and the protective buffer layer, with the conductive structure not being formed over the via structure. Thus, deterioration of the conductive and via structures is minimized. | 2011-12-29 |
20110318924 | METHOD FOR DEPOSITION OF AT LEAST ONE ELECTRICALLY CONDUCTING FILM ON A SUBSTRATE - The invention relates to a method for deposition of at least one electrically conducting film ( | 2011-12-29 |
20110318925 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing method includes applying electroless plating of CoWB onto a Cu interconnection line formed on a wafer W, and then performing a post-cleaning process by use of a cleaning liquid on the target substrate or wafer before a by-product is precipitated on the surface of the CoWB film formed by the electroless plating to cover the Cu interconnection line. | 2011-12-29 |
20110318926 | Wiring structure, semiconductor device and manufacturing method thereof - A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film. | 2011-12-29 |
20110318927 | Multiple Patterning Lithography Using Spacer and Self-Aligned Assist Patterns - The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing. | 2011-12-29 |
20110318928 | Polymeric Barrier Removal Polishing Slurry - The invention provides a aqueous slurry useful for chemical mechanical polishing a semiconductor substrate having copper interconnects. The slurry comprises by weight percent, 0 to 25 oxidizing agent, 0.1 to 50 abrasive particles, 0.001 to 10 inhibitor for decreasing static etch of the copper interconnects, 0.001 to 5 poly(methyl vinyl ether) having a formula as follows: | 2011-12-29 |
20110318929 | CMP POLISHING SOLUTION AND POLISHING METHOD - The CMP polishing solution of the invention comprises (A) a metal corrosion inhibitor containing a compound with a 1,2,3-triazolo[4,5-b]pyridine skeleton, (B) an abrasive grain having a positive zeta potential in the CMP polishing solution, (C) a metal oxide solubilizer and (D) an oxidizing agent. The polishing method of the invention comprises a first polishing step in which the conductive substance layer of a substrate comprising an interlayer insulating filth having an elevated section and a trench at the surface, a barrier layer formed following the surface of the interlayer insulating film and the conductive substance layer formed covering the barrier layer, is polished to expose the barrier layer located on the elevated section of the interlayer insulating film, and a second polishing step in which the barrier layer exposed in the first polishing step is polished using the CMP polishing solution to expose the elevated section of the interlayer insulating film. | 2011-12-29 |
20110318930 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate. | 2011-12-29 |
20110318931 | Method of Forming a Micro-Pattern for Semiconductor Devices - Methods of forming integrated circuit devices utilize fine width patterning techniques to define conductive or insulating patterns having relatively narrow and relative wide lateral dimensions. A target material layer is formed on a substrate and first and second mask layers of different material are formed in sequence on the target material layer. The second mask layer is selectively etched to define a first pattern therein. Sidewall spacers are formed on opposing sidewalls of the first pattern. The first pattern and sidewall spacers are used collectively as an etching mask during a step to selectively etch the first mask layer to define a second pattern therein. The first pattern is removed to define an opening between the sidewall spacers. The first mask layer is selectively re-etched to convert the second pattern into at least a third pattern, using the sidewall spacers as an etching mask. The target material layer is selectively etched using the third pattern as an etching mask. | 2011-12-29 |
20110318932 | Pyrolysis Methods, Catalysts, and Apparatuses for Treating and/or Detecting Gas Contaminants - Processes for treating gas streams contaminated with fluorine-containing compounds, in addition to apparatuses for such treatment processes that may also be used to monitor the emission of these compounds, are disclosed. In the processes and apparatuses, catalytic conversion (pyrolysis) one or more fluorine-containing contaminants (e.g., perfluorocarbon) in the gas stream is carried out using a catalyst comprising tungstated zirconia or sulfated zirconia. The catalysts exhibit exceptional responsiveness, recovery, and/or activity, compared to conventional catalysts, for this purpose. | 2011-12-29 |
20110318933 | SUBSTRATE PROCESSING METHOD - There is provided a substrate processing method capable of preventing the decrease in etching efficiency by positive ions and increasing the overall etching efficiency by using negative ions. The substrate processing method includes applying a plasma RF and a bias RF in the pattern of a pulse wave, respectively. The substrate processing method repeatedly performs the steps of: ( | 2011-12-29 |
20110318934 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes a chamber accommodating a wafer, a susceptor disposed inside the chamber and on which the wafer is held, an upper electrode facing the susceptor, and a second high frequency power source connected to the susceptor, wherein the upper electrode is electrically connected to a ground and is moveable with respect to the susceptor. The substrate processing apparatus divides a potential difference between plasma generated in a processing space and the ground into a potential difference between the plasma and a dielectric and a potential difference between the dielectric and the ground by burying the dielectric in the upper electrode, and changes a gap between the upper electrode and the susceptor. Accordingly, plasma density between the upper electrode and the susceptor is changed | 2011-12-29 |
20110318935 | METHOD OF SETTING THICKNESS OF DIELECTRIC AND SUBSTRATE PROCESSING APPARATUS HAVING DIELECTRIC DISPOSED IN ELECTRODE - Provided is a method of setting a thickness of a dielectric, which restrains the dielectric formed in an electrode from being consumed when etching a silicon dioxide film on a substrate by using plasma. In a substrate processing apparatus including an upper electrode facing a susceptor and the dielectric formed of silicon dioxide in the upper electrode, a silicon dioxide film formed on a wafer being etched by using plasma, an electric potential of the plasma facing the dielectric in a case where the dielectric is not formed in the upper electrode is estimated based on a bias power applied to the susceptor and an A/C ratio in a chamber, and the thickness of the dielectric is determined so that an electric potential of the plasma, which is obtained by multiplying the estimated electric potential of the plasma by a capacity reduction coefficient calculated when a capacity of the dielectric and a capacity of a sheath generated around a surface of the dielectric are combined, is 100 eV or less. | 2011-12-29 |
20110318936 | Etch process for reducing silicon recess - A method for selectively etching a substrate is described. The method includes disposing a substrate comprising a silicon nitride (SiN | 2011-12-29 |
20110318937 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, METHOD OF CLEANING A PROCESS VESSEL, AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device includes supplying a process gas into a process vessel accommodating a substrate to form a thin film on the substrate and supplying a cleaning gas into the process vessel to clean an inside of the process vessel, after the supplying the process gas to form the thin film is performed a predetermined number of times. When cleaning the inside of the process vessel, a fluorine-containing gas, an oxygen-containing gas and a hydrogen-containing gas are supplied as the cleaning gas into the process vessel heated and kept at a pressure less than an atmospheric pressure to remove a deposit including the thin film adhering to the inside of the process vessel through a thermochemical reaction. | 2011-12-29 |
20110318938 | TEMPORARY BONDING ADHESIVE FOR A SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - To provide a temporary bonding adhesive for a semiconductor wafer that reduces damage to a semiconductor wafer, makes it readily detachable, and can shorten the time required for thermal decomposition, and a manufacturing method for a semiconductor device using this.
| 2011-12-29 |
20110318939 | HIGH ORDER SILANE COMPOSITION AND METHOD OF MANUFACTURING A FILM-COATED SUBSTRATE - A composition comprising a high order silane compound and a solvent, wherein the solvent contains a cyclic hydrocarbon which has one or two double bonds and no alkyl group, is composed of only carbon and hydrogen and has a refractive index of 1.40 to 1.51, a specific permittivity of not more than 3.0 and a molecular weight of not more than 180. | 2011-12-29 |
20110318940 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device includes forming a layer containing a predetermined element on a substrate by supplying a source gas containing the predetermined element into a process vessel and exhausting the source gas from the process vessel to cause a chemical vapor deposition (CVD) reaction. A nitrogen-containing gas is supplied into the process vessel and then exhausted, changing the layer containing the predetermined element into a nitride layer. This process is repeated to form a nitride film on the substrate. The process vessel is purged by supplying an inert gas into the process vessel and exhausting the inert gas from the process vessel between forming the layer containing the predetermined element and changing the layer containing the predetermined element into the nitride layer. | 2011-12-29 |
20110318941 | Composition and Method of Forming an Insulating Layer in a Photovoltaic Device - A solar cell includes a first electrode located over a substrate, at least one p-type semiconductor absorber layer located over the first electrode, the p-type semiconductor absorber layer comprising a copper indium selenide (CIS) based alloy material, an n-type semiconductor layer located over the p-type semiconductor absorber layer, an insulating aluminum zinc oxide layer located over the n-type semiconductor layer, the insulating aluminum zinc oxide having an aluminum content of 100 ppm to 5000 ppm and a second electrode over the insulating aluminum layer, the second electrode being transparent and electrically conductive. The insulating aluminum zinc oxide having an aluminum content of 100 ppm to 5000 ppm, may be deposited by pulsed DC, non-pulsed DC, or AC sputtering from an aluminum doped zinc oxide having an aluminum content of 100 ppm to 5000 ppm. | 2011-12-29 |
20110318942 | MECHANICALLY ROBUST METAL/LOW-k INTERCONNECTS - A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material. | 2011-12-29 |
20110318943 | SOCKET CONNECTOR ASSEMBLY HAVING REINFORCING MEMBER FOR SUPPORTING LOADING DEVICE - A loading device comprises a frame defining opposite top, bottom face, and a number of mounting holes extending through both the faces; a loading plate and a lever pivotally connected on the frame respectively, the loading plate being able to be locked on the frame by the lever; a number of screw members passing through corresponding mounting holes; a number of connecting members located below the bottom face of the frame and engaging with corresponding screw member; and a number of reinforcing members disposed between the bottom face and the connecting members for limiting movement of the frame relative to the connecting members. | 2011-12-29 |
20110318944 | Probe Connector - A probe connector has a base. The base has a plurality of through inserting holes at a front surface thereof. A rear surface of the base has a plurality of fixing slots, each of which extends at a side of the inserting hole and communicates with the corresponding inserting hole. A probe pin assembly has a barrel received in the inserting hole, an elastic element, and a plunger. An outer peripheral surface of the barrel is formed with a fixing recess. A conduct element has a base plate attached to a bottom surface of the base and a locking plate extended from the base plate and attached to the rear surface. The locking plate has at least one locking opening, corresponding to the inserting hole, and two opposite sides extended forwards to form two fixing slices received in the fixing slots, with free ends thereof buckled in the fixing recess. | 2011-12-29 |
20110318945 | ELECTRICAL CONNECTOR WITH GROUND PLATES - An electrical connector and leadframe assemblies for use therein are provided. Each leadframe assembly can be constructed with at least one electric contact having a ground plate. A first type of leadframe assembly includes an uppermost electrical contact defining a ground plate. A second type of leadframe assembly includes a lowermost electrical contact defining a ground plate. The ground plates can reduce the level of crosstalk exhibited by the electrical connector. | 2011-12-29 |
20110318946 | Integrated Planar Electrical Connector For Personal Electronic Devices - A planar electrical connector is configured to be stowed within a personal electronic device. The planar electrical connector comprises a connector housing having a moveable support structure. The moveable support structure is configured to permit movement of the planar electrical connector relative to the personal electronic device between a use position and a stowed position. The connector housing configured to define a single plane of contact within a charging receptacle and support a positive electrical contact and a negative electrical contact. | 2011-12-29 |
20110318947 | UNLOCKING DEVICE, CONNECTOR DEVICE, AND CONNECTOR | 2011-12-29 |
20110318948 | Universal Foot Switch Contact Port - A universal contact port for receiving contacts of various cross-sectional dimensions and cross-sectional profiles of an electrosurgical component is provided. The universal contact port includes a plurality of rollers each defining a corporal axis, the corporal axes being at least substantially parallel to one another; and a plurality of shafts eccentrically supporting a respective roller, each shaft defining a longitudinal axis, wherein each corporal axis is spaced a radial distance from a respective longitudinal axis and wherein the rollers are rotatable about the longitudinal axes. The rollers define an opening therebetween, wherein the opening is expandable and constrictable upon rotation of the rollers about the longitudinal axes, whereby the contact port can accommodate receipt of contacts, from electrosurgical components, of varying cross-sectional diameter therein. | 2011-12-29 |
20110318949 | Modular Connector - A modular connector is provided comprising: a connector plug, which may be inserted into an associated socket in a first longitudinal direction; a resilient leg, depending at a first end thereof from the connector plug, and having a depressible part, distal therefrom, depressible towards the connector plug; and a guard cover, configured to prevent access to the depressible part of the resilient leg in its direction of depression, but to permit access to the resilient leg in the longitudinal direction through an access aperture, the access aperture being aligned with the depressible part of the resilient leg on an axis parallel with the longitudinal direction, to allow depression of the resilient leg through the access aperture directly. A corresponding extraction tool and methods, loopback connector, blanking plug, blanking plate and patch panel are also provided. | 2011-12-29 |
20110318950 | CHARGING CONNECTOR - A charging connector ( | 2011-12-29 |
20110318951 | POWER INPUT ELECTRICAL CONNECTOR - A wiring harness electrical connector is provided having a detachable and re-attachable mounting system to permit the attachment of the connector on a frame surface of a semi-trailer, or workpiece, from the rear or interior side of the of the frame or workpiece without disruption to the integrally formed and moisture proof encasing of the connector. | 2011-12-29 |
20110318952 | PLUG MODULE - A plug module disposed at the end of a cable is used for assembling in a socket, and the socket has a connecting portion and a position limiting structure on the connecting portion. The plug module includes a body, a positioning element, and a sliding element. The body is connected with the connecting portion in a connecting direction. The positioning element disposed on the body is interfered the position limiting structure. The sliding element is slidingly disposed at a side of the body adjacent to the cable, and it is suited for driving the positioning element to release the interference between the positioning element and the position limiting structure. | 2011-12-29 |
20110318953 | SHEAR FASTENER - The present invention relates to a shear fastener for an electrical connector. The fastener includes a head from which a threaded shaft extends. The head defines a pair of polygonal portions separated by a recess so that an endmost one of the polygonal portions can be separated from the fastener by shearing as the fastener is tightened within the connector. Separation of opposite flats of the endmost polygonal portion is different (e.g. greater) than separation of opposite flats of the other polygonal portion. In one embodiment, the engagement socket of a pneumatic wrench can slip over the polygonal portions and rotate through 360° when rapidly tightening the fastener whilst engaging with the endmost polygonal portion, without engaging with the other polygonal portion. | 2011-12-29 |
20110318954 | SOCKET STRUCTURE OF MINIATURE LIGHT BULB SET - A socket assembly is provided for a miniature light bulb set, including a socket body, a base member that receives power cords set thereon, and a holder that receives and holds a light bulb. The socket body has a bottom portion having front and rear sides forming cord cavities each of which forms a rim to form the structure for positioning and retaining the cord. The base member has left and right sidewalls each forming a retention block that projects outwards and has an increased thickness of material for forming the structure for coupling with the socket body. | 2011-12-29 |
20110318955 | Connector, Receptable, and Connector Assembly for Digital Band - Disclosed are a digital band connector, a receptacle, and a connector assembly for easily connecting digital bands formed of digital yarns to an external circuit. The digital band connector includes connect pins spaced apart from each other in a direction, passing through the digital bands made of digital yarns and to fix the digital bands, and electrically connected with the digital bands, a lower housing fixing the digital bands and the connect pins in a lower part and exposing one end of each of the connect pins through a lower surface, and an upper housing coupled with an upper part of the lower housing to fix the digital bands and the connect pins. | 2011-12-29 |
20110318956 | DUAL STACKED CONNECTOR - A connector has a housing and two edge card-receiving slots disposed in a stacked arrangement on a first face of the housing. The housing supports a plurality of wafers, each wafer supporting a plurality of terminals and including two grooves, the grooves aligned with the terminals supported by the wafer. The housing may be positioned in a cage that includes receptacles on a front face of the cage. A light pipe may extend toward the front face of the cage. | 2011-12-29 |
20110318957 | SNAP-ON SWITCH MODULE ASSEMBLY - A snap-on switch module assembly includes a plug connector adapted to be received by an electrical device. A second housing is connected to a first housing. A switch device is disposed between the first and second housings. At least one first opening is formed in the second housing. A plurality of wires pass through the at least one first opening and are connected to the switch device. Accordingly, the switch device protects and controls electrical apparatus connected to the electrical device. | 2011-12-29 |
20110318958 | COAXIAL CONNECTOR WITH DUAL-GRIP NUT - A connector for coaxial cable includes a dual-grip nut having a first external gripping surface and a second external gripping surface. The smallest outer diameter of the first external gripping surface is less than the smallest outer diameter of the second external gripping surface. | 2011-12-29 |
20110318959 | Coaxial Connector - A coaxial connector | 2011-12-29 |
20110318960 | CONTACT FOR COAXIAL CABLE AND END PROCESSING METHOD FOR COAXIAL CABLE - A contact for coaxial cable attached to an end of a coaxial cable includes a contact part and a connection part. The connection part includes a conductor barrel, an open crimp barrel, and a junction band narrow in width. The conductor barrel is disposed on a side to a base end portion of the contact part and can crimp the inner conductor. The open crimp barrel is adjacent to the conductor barrel and can crimp an exposed portion of the dielectric body so as to surround the exposed portion of the dielectric body in a cylindrical shape. The junction band joins the conductor barrel with the open crimp barrel so as to bridge the two. The both end portions of the junction band are torn during or after crimping of the conductor barrel and the open crimp barrel. | 2011-12-29 |
20110318961 | ELASTIC CONNECTOR, METHOD OF MANUFACTURING ELASTIC CONNECTOR, AND ELECTRIC CONNECTION TOOL - The present invention provides technology with high production efficiency for an elastic connector that electrically connects two connection target members. The technology enables an initial product to be quickly completed with a low initial cost, in correspondence to any distance between the connection target members and any angle formed between them. An elastic connector was obtained by forming a major-axis columnar body, in which a conductive part was formed by cross linking and hardening (solidifying) conductive members inside a tube-like part formed of an insulative rubber tube, and then cutting the major-axis columnar body with a cutting blade along a cutting line, which is in a direction crossing the axis of the major-axis columnar body, to shorten the major-axis columnar body. This elastic connector eliminates the need to create a new metal mold in its manufacturing. When a length to which the major-axis columnar body is cut is appropriately changed and it is cut to that length, an elastic connector that suit any distance between the connection target members and any angle formed between them can be obtained. | 2011-12-29 |
20110318962 | SIGNAL TRANSMISSION FOR HIGH SPEED INTERCONNECTIONS - A connector assembly includes a substrate and a connector. The substrate includes a ground layer and a trace layer. The substrate defines a substrate edge, and the ground layer defines a ground edge. The connector is mounted on the substrate such that a portion of the connector overhangs the substrate edge of the substrate. The connector includes a first signal contact that defines a mating portion, a mounting portion, a first transition portion connected to the mating portion, and a second transition portion connected to the first transition portion and the mounting portion. The first transition portion of the signal contact at least partially crosses the ground edge such that a gap is defined between the ground edge and the first transition portion and a substantial portion of the second transition portion extends over the gap when the electrical connector is mounted on the substrate. | 2011-12-29 |
20110318963 | SHIELD CONNECTOR - A metal shell includes a pair of side face shield walls for respectively covering both side faces of a housing and a coupling shield wall perpendicular to the side face shield walls and coupling the side face shield walls together, and covers the circumference of the housing. A metal slider is movably attached to at least one of the housing and the shell while coming into slidable contact therewith. The slider electrically connects contacts and conductors of a flexible conductive member and is electrically connected to the shell and a shield portion exposed on the surface of the flexible conductive member, in a state where the slider has moved from the rear side toward the front side with respect to the housing. | 2011-12-29 |
20110318964 | CARD DESIGN WITH FULLY BUFFERED MEMORY MODULES AND THE USE OF A CHIP BETWEEN TWO CONSECUTIVE MODULES - An AMB component and a connection interface for a memory installation with fully buffered Dimm memory modules connected in series. The AMB component is disposed on a connecting line from memory modules to a memory controller of the memory installation to re-amplify the connecting line between two consecutive FBD memory modules. The connection interface includes an AMB amplifier component for the connection of a main memory card that includes at least one processor, to an auxiliary memory card of the type having a series of memory modules. Two series of FBD memory modules are connected to respective FBD channels in the auxiliary memory card using FBD connectors in a daisy-chain arrangement. | 2011-12-29 |
20110318965 | TELECOMMUNICATIONS DEVICE - The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack. | 2011-12-29 |
20110318966 | Electrical Connector and Conductive Member Thereof - An electrical connector and a conductive member thereof are provided. In one embodiment of the present invention, the conductive member is installed in an insulating body, and a solder ball is retained between two retaining ends of the conductive member to form the electrical connector. In the conductive member, a base extends downwards to form two soldering arms, each of the soldering arms has an extending arm and a retaining end extending from the extending arm, the retaining ends are exposed outside the insulating body, and at least one of the retaining ends is provided with a recessed portion, so as to enable the solder ball, when entering between the two retaining ends, to prop the two retaining ends and partially enter the recessed portion, so that the solder ball is securely retained by the two retaining ends, thereby preventing the solder ball from falling off from the two retaining ends when the electrical connector is under an external force. | 2011-12-29 |
20110318967 | CARD CONNECTOR - The card connector, into which an IC card having a plurality of pads arranged in parallel at front and back positions is inserted, includes a plurality of contacts each contacting a corresponding one of the plurality of pads of the IC card and a base member that supports the plurality of contacts. Each of the plurality of contacts has a first and a second elastic piece each having a contact point portion that electrically contacts a pad of the IC card. The first and second elastic pieces are formed such that contact pressures of the respective contact point portions against the pads are different from each other. The plurality of contacts is arranged on the base member in parallel at front and back positions and a first and a second contact piece are arranged in an opposite manner in contacts aligned linearly at front and back positions. | 2011-12-29 |
20110318968 | ELECTRICAL CONNECTOR FOR IMPROVING INTENSITY OF CONTACTS - An electrical connector includes an insulative housing defining a plurality of passageways extending in a mating direction and a plurality of contacts secured in the passageways of the insulative housing. The insulative housing further defines a plurality of communicating slots extending downwardly and communicating with the passageways. Each passageway is wider than the communicating slot which is thereabove. Each contact defines a connecting portion receiving in the passageway and a contacting portion bending upwardly from the connecting portion and extending beyond the communicating slot. The connecting portion defines a pair of restricting portions respectively extending from two sides thereof in a direction perpendicular to the mating direction, the pair of restricting portions is prevented in the passageway from extending beyond the communicating slot. | 2011-12-29 |
20110318969 | CONNECTOR - A connector fixable on a board comprises a plurality of plug contacts and a plurality of receptacle contacts, wherein the plug contacts and the receptacle contacts are alternately arranged on a fit plane. | 2011-12-29 |
20110318970 | TELECOMMUNICATIONS DEVICE - The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack. | 2011-12-29 |
20110318971 | ELECTRICAL CONNECTOR ASSEMBLY WITH ANTI-MISMATCHING MATING CONNECTORS - An exemplary electrical connector assembly includes an insert connector and a receiving connector. The insert connector includes a first pin and a second pin. The receiving connector defines a first and a second holes corresponding to the first and second pins of the insert connector, respectively. The first hole has a shape and a size matching the first pin, and the second hole has a shape and a size matching the second pin. The first and second pins of the insert connector are respectively extendable into and engagable in the first and second holes of the receiving connector. A transverse cross sectional area of the second pin is larger than that of the first pin, whereby the second pin of the insert connector is prevented from being received in the first through hole of the receiving connector. | 2011-12-29 |
20110318972 | CONNECTING TERMINAL - A connecting terminal ( | 2011-12-29 |
20110318973 | Receptacle Connector - A receptacle connector includes a body; a conductive member received in the body and having a bottom, in which a soldering portion extends from the bottom, the bottom is bent upwards to form a base, an angle is formed between the planes of the base and the bottom, two opposing sides of the base are bent to form a first arm and a second arm, the first and second arms are on the same side and are in the same direction as a bending direction of the base, the first arm has a first contact portion, and the second arm has a second contact portion; and a third arm extending from one end of the base away from the bottom, inclined towards the first and second arms, in which the inclination of the third arm does not exceed initial contact positions of the first and second arms with a pin, the third arm has a third contact portion, and the first, second and third contact portions are used for jointly retaining and contacting the pin. | 2011-12-29 |
20110318974 | Spring-Loaded Compression Electrical Connector - A connector having a spring inserted internally in a compression or crimp connector, or in a bolted compression connector, in contact with the electrical conductors to be connected electrically wherein the spring is capable of being mechanically deformed during compression of the connector and wherein the spring is capable of maintaining its elastic resilience and elastic springback properties to generate and maintain the required compression force on the conductor. The spring may be a metal mechanical spring or formed of a resiliently flexible material, particularly a polymeric material. | 2011-12-29 |
20110318975 | Contact Clamp and Connector Having Contact Clamp - The invention relates to a contact clamp for connecting a conductor end with an electrical contact and having an insertion side, from which the conductor end can be inserted in the contact clamp, comprising a retaining frame with a contact section, with which the conductor end can establish a contact, as well as a clamping leg, which is pivotally mounted in the retaining frame and can be pivoted back and forth between an open pivot position (FIG. | 2011-12-29 |
20110318976 | UNIVERSAL TERMINATION SYSTEM FOR POWER TOOLS - A universal termination system is provided for power tools. The universal termination system includes criteria for each of the main switch platforms that define the number, type, location and orientation of the terminations. That is, the number, type, location and orientation of the terminations in each main switch platform are standardized and the power tools that use that type main switch platform use the main switch platform having the standardized terminations. That is, power tools that use push button switches use the push button switch with the standardized terminations, power tools that use overhang switches use the overhang switch with the standardized terminations, and power tools that use in-line VSR switches use the in-line VSR switch with the standardized terminations. In an aspect of the invention, a right-angle pin terminal is received in one or more sets of the standardized terminations. In an aspect of the invention, the switch body has features that cooperate with the right-angle pin terminals to reduce the risk of shorting adjacent terminals. In an aspect of the invention, a switch has standardized connections on a bottom of a switch body that mate with terminals of a plug-in control module. In an aspect of the invention, a switch for a hand-held power tool has cord set terminations that are screw-tab terminals. | 2011-12-29 |
20110318977 | MARINE VESSEL PROPULSION APPARATUS - A marine vessel propulsion apparatus includes an engine, a rotation speed detecting device, a forward-reverse switching mechanism, a shift position detecting device, a liquid supplying device, a flow passage, a physical quantity detecting device, and a controller. The flow passage is arranged such that a liquid is supplied from the liquid supplying device when a crankshaft is rotating in one rotation direction. A physical quantity of the liquid in the flow passage after the forward-reverse switching mechanism has been switched from the forward drive state to the reverse drive state in a state where the crankshaft is rotating is a post-switching physical quantity. The controller executes a reverse rotation prevention control to control at least one of either the engine or the forward-reverse switching mechanism to prevent reverse rotation of the crankshaft in a case where the post-switching physical quantity is less than a predetermined first value. | 2011-12-29 |
20110318978 | MODULAR GONDOLA DRIVE FOR A FLOATING DEVICE - A gondola drive for a floating device has an underwater housing circulated around by water. The gondola drive contains a drive module which has a drive module housing and a shaft disposed therein, a transmission module with a transmission module housing and a transmission disposed therein and a propeller. The drive module and the transmission module are each configured as separate components connected to one another such that the drive module housing and the transmission module housing form at least a part of the underwater housing and that the shaft is coupled to the transmission for driving the propeller. | 2011-12-29 |
20110318979 | WATER-SPORT BOARDING APPARATUS - According to one embodiment of the invention, a water-sport boarding apparatus is provided, comprising an elongated hoard including: a top surface, a bottom surface, and an outer edge, wherein a first end segment of the elongated board comprises a first half-circle portion of the outer edge, a second end segment of the elongated board comprises a second half-circle portion of the outer edge, a middle segment of the elongated board unifies the first end segment with the second end segment, the middle segment comprises two substantially linear portions of the outer edge, the top surface is substantially flat, the bottom surface under the middle segment is convex along the width of the elongated board, and the bottom surface comprises a plurality of elongated ridges disposed parallel to a length of the elongated board, the elongated ridges forming a water channel on the bottom surface along the length of the elongated hoard. | 2011-12-29 |
20110318980 | DROP-KNEE BOARD - The present invention describes a versatile drop-knee board having a fore section and an aft section suitable for wave boarding. The multi-purpose board of the present invention is provided with an aft section having crotch-sized width in order to allow a user's legs to kick within a general lateral outline of a wider fore section. The combination board can be utilized for surfboarding (both legs standing), drop-knee boarding (one leg standing and one knee down) or body boarding (body prone), preferably while wearing swim fins on the feet. | 2011-12-29 |
20110318981 | COMPOSITE MATERIAL STRUCTURE PROTECTED AGAINST THE EFFECTS OF LIGHTNING - The invention relates to a part ( | 2011-12-29 |
20110318982 | LIQUID CRYSTAL POLYESTER FIBERS AND METHOD FOR PRODUCING THE SAME - Disclosed are liquid crystal polyester fibers, which have a peak half-width of 15° C. or greater at an endothermic peak (Tm1) observed by differential calorimetry under a temperature elevation of 20° C./minute from 50° C., polystyrene equivalent weight average molecular weight of 250,000 or more and 2,000,000 or less, and a variable waveform of less than 10% in terms of the half inert diagram mass waveform determined by a Uster yarn irregularity tester. Also disclosed is a method for producing liquid crystal polyester fibers, wherein liquid crystal polyester fibers are formed into a package, the fibers are then subjected to solid-phase polymerization, and the solid-phase polymerized liquid crystal polyester fibers are unrolled from the package and successively heat treated without being once taken up. The heat treatment temperature is controlled at a temperature of the endothermic peak temperature (Tm1) of the solid-phase polymerized liquid crystal polyester fibers+60° C. or higher, and the speeds of the fibers before and after heat treatment are regulated, respectively, by first and second rollers. | 2011-12-29 |