Entries |
Document | Title | Date |
20100287522 | Method and Apparatus for Automated Synthesis of Multi-Channel Circuits - Methods and apparatuses to time-share resources having internal states are described. A first design of a system having a plurality of instances of a logical block to perform logical operations is received. The instances may have internal states. The system is automatically transformed to generate a second design having a fewer quantity of time-shared instances of the logical block. The plurality of the instances in the first design is replaced with the fewer time-shared instances in the second design. The time-shared instances in the second design have elements to time multiplex the internal states. | 11-11-2010 |
20110035710 | DESIGN SUPPORT PROGRAM, DESIGN SUPPORT DEVICE, AND DESIGN SUPPORT METHOD - A design support program stored in a computer readable recording medium and executed by the computer includes computer readable program code stored thereon for causing a computer to execute operations of: selecting a first hierarchy which has different first characteristic information included in wiring layer structure information in a storage device; generating second characteristic information including the first characteristic information; copying wiring layer structure information; and converting the first characteristic information included in the copied wiring layer structure information into the second characteristic information to obtain a converted wiring layer structure information. | 02-10-2011 |
20110066986 | TOKEN ENHANCED ASYNCHRONOUS CONVERSION OF SYNCHONOUS CIRCUITS - A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output. | 03-17-2011 |
20110154277 | METHOD AND APPARATUS FOR GENERATING SUBSTRATE LAYOUT - Embodiments of the invention discuss methods and apparatus for efficiently generating substrate layout for motherboards and packages having high pin-count processors. The method comprises: extracting layout objects associated with a motherboard having a processor; identifying a type for each of the extracted layout objects; reordering the extracted layout objects based on the identified types for each of the extracted layout objects; grouping the layout objects based on the identified types; and generating a motherboard design based on the grouped layout objects. | 06-23-2011 |
20110154278 | DECISION MODULES - An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. | 06-23-2011 |
20110154279 | DECISION MODULES - An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified. | 06-23-2011 |
20110161898 | Synthesizing Checkers from Nondeterministic Finite Automaton - The present invention provides for the generation of non-deterministic checker circuits. for use in formal verification of electronic designs. In various implementations, an assertion is first received, subsequently; a failure sequence is derived from the assertion. After which, a non-deterministic finite automaton is derived from the failure sequence. Lastly, a checker circuit is generated directly from the non-deterministic finite automaton. | 06-30-2011 |
20110219344 | Spatial Correlation-Based Estimation of Yield of Integrated Circuits - Techniques for estimating yield of an integrated circuit design, such as a very-large-scale integration (VLSI) design, are provided. In one aspect, a method for determining a probability of failure of a VLSI query design includes the following steps. A Voronoi diagram is built comprising a set of shapes that represent the design. The Voronoi diagram is converted into a rectangular grid comprising 2 | 09-08-2011 |
20110225556 | PACKAGE SUBSTRATE DESIGN DEVICE, PACKAGE SUBSTRATE DESIGN METHOD, AND COMPUTER READABLE RECORDING MEDIUM FOR RECORDING PACKAGE SUBSTRATE DESIGN PROGRAM - According to one embodiment, a package substrate design device includes a first wiring module, a net generator, a second wiring module, and a third wiring module. The first wiring module is configured to generate a plurality of first vias configured to connect wires on the first wiring layer and wires on the second wiring layer and configured to generate a plurality of first wires configured to connect the first vias and the first terminals. The net generator is configured to generate nets for connecting the second terminals and k-th (k is an integer of 1 to (n−2)) vias. The second wiring module is configured to generate a plurality of (k+1)-th vias configured to connect wires on the (k+1)-th wiring layer and wires on the (k+2)-th wiring layer and configured to generate a plurality of (k+1)-th wires configured to connect the (k+1)-th vias and the k-th vias, the (k+1)-th vias and the (k+1)-th wires being generated between the k-th vias and the second terminals connected by the nets. The third wiring module is configured to generate a plurality of n-th wires configured to connect the (n−1)-th vias and the second terminals. | 09-15-2011 |
20110225557 | HIGH-LEVEL SYNTHESIS APPARATUS, HIGH-LEVEL SYNTHESIS METHOD, AND COMPUTER READABLE MEDIUM - A high-level synthesis apparatus includes an internal representation generator, a scheduler, a frequency controller, an allocator, a register transfer level description generator, and an outputting module. The internal representation generator generates internal representation from behavioral description of a semiconductor integrated circuit. The scheduler schedules arithmetic operations in the internal representation. The frequency controller changes a clock frequency of the semiconductor integrated circuit based on a result of the scheduler. The allocator fixes a circuit configuration of the semiconductor integrated circuit behaving at the changed clock frequency. The register transfer level description generator generates register transfer level description from the internal representation based on a result of the allocator. The outputting module outputs the register transfer level description. | 09-15-2011 |
20110225558 | RECONFIGURABLE CIRCUIT GENERATION DEVICE, METHOD, AND PROGRAM - A reconfigurable circuit generation device comprises: a netlist generation unit that generates as a shared netlist a netlist that can be shared among a plurality of netlists having a common portion, and a resource reduction unit that reduces resources of the reconfigurable circuit where the plurality of netlists are to be implemented, in a range in which the shared netlist can be implemented. | 09-15-2011 |
20110258587 | SIGNAL DELAY SKEW REDUCTION SYSTEM - A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist. | 10-20-2011 |
20110265050 | REPRESENTING BINARY CODE AS A CIRCUIT - A high level intermediate representation of a binary is generated. Circuit nodes from the high level intermediate representation are built, wherein a circuit node represents an operation in the high level intermediate representation. The circuit nodes are connecting using a flow analysis of the binary to build a circuit that represents the binary. | 10-27-2011 |
20110271242 | Efficient Redundancy Identification, Redundancy Removal, and Sequential Equivalence Checking within Designs Including Memory Arrays - A mechanism is provided for efficient redundancy identification, redundancy removal, and sequential equivalence checking with designs including memory arrays. The mechanism includes an array merging component to optimally merge an array output such that if the address is out-of-bounds or the port is not asserted, the array output is converted to a random output. The mechanism also includes a component for determining the equivalence of enabled array outputs rather than the array outputs directly and creating an enabled array output. The mechanism also includes a component that precludes potentially-redundant array cells from participating in the sequential redundancy removal determination. This component first checks for compatibility of the corresponding arrays, then the corresponding read port enables and addresses, then the corresponding initial values, and finally checking that writes to the corresponding columns yield a compatible set of values. | 11-03-2011 |
20110307847 | Hybrid system combining TLM simulators and HW accelerators - A hybrid system is combining transaction level modeling (TLM) simulators and hardware accelerators so that new system-on chip (SoC) designs are integrated in a virtual platform (VP) to run TLM simulation and existent semiconductor intellectual properties (IP) are added to physical platform (PP) to run hardware accelerator. A new circuit design with TLM is easier to be performed than with register transfer language (RTL) and it is integrated in a virtual platform and existent IP doesn't have to be redesigned to be integrated in a virtual platform. | 12-15-2011 |
20110307848 | METHOD FOR PREPARING FOR AND FORMALLY VERIFYING A MODIFIED INTEGRATED CIRCUIT DESIGN - A method for preparing an IC design that has been modified to be formally verified with a reference IC design. Because some formal verification tools cannot handle the complexity often associated with sequential equivalence checking at the top level of a circuit, the modified IC design may be instantiated into a number of different design versions, each having different levels of modification complexity. In addition, the reference IC design and the modified versions may be decomposed into a datapath and control path. The reference IC design and each of the modified IC design versions may also use wrappers to encapsulate various levels of hierarchy of the logic. Lastly, rather than having to verify each of the modified versions back to the reference IC design, the equivalence checking may be performed between each modified IC design version and a next modified IC design version having a greater modification computational complexity. | 12-15-2011 |
20110320991 | HIERARCHIAL POWER MAP FOR LOW POWER DESIGN - A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result. | 12-29-2011 |
20120011480 | Logic-Driven Layout Verification - A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data. | 01-12-2012 |
20120036488 | Method and Apparatus for Automatic Relative Placement Rule Generation - Methods and apparatuses are disclosed that automatically generate relative placement rules. Constructs at the register transfer language-level result in relative placement rules specified at the register transfer language-level. | 02-09-2012 |
20120079438 | INTEGRATED CIRCUIT DESIGN FRAMEWORK COMPRISING AUTOMATIC ANALYSIS FUNCTIONALITY - An embodiment of an integrated circuit design framework comprises a user interface which automatically initializes a three-dimensional simulation tool for simulating or analyzing the characteristics of a complex metallization system. In some illustrative embodiments the user interface may additionally provide electrically simulated parameter values for an input parameter, such as the channel resistance of a power transistor, thereby enabling a simulation of a portion of interest of the metallization system without actually requiring the provision of the design data of the power transistor. | 03-29-2012 |
20120096417 | INTEGRATED DATA MODEL BASED FRAMEWORK FOR DRIVING DESIGN CONVERGENCE FROM ARCHITECTURE OPTIMIZATION TO PHYSICAL DESIGN CLOSURE - Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; encoding architecture level knowledge in a data model to generate and pass new constraints for physical synthesis of a chip specification uniquely customized to the computer readable code; receiving a look-ahead cost function during architecture optimization consistent with cost observed later in the flow after detailed physical synthesis is performed, wherein the look-ahead cost function is generated from a prior iteration and supplied to a subsequent iteration through the data model; automatically translating information available at one optimization point into a constraint for another optimization point invoked at a different place in the design flow using the data model; and synthesizing a computer readable description of the chip specification into the custom integrated circuit for semiconductor fabrication. | 04-19-2012 |
20120117525 | Translating a User Design in A Configurable IC for Debugging the User Design - Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design. | 05-10-2012 |
20120131524 | METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY - A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels. | 05-24-2012 |
20120159406 | TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS WITH REPRODUCIBLE TRANSFORMS - A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence. | 06-21-2012 |
20120159407 | Low Depth Circuit Design - A method of designing a logic circuit based on one of the functions of the form f | 06-21-2012 |
20120167022 | METHOD AND DEVICE FOR IDENTIFYING AND IMPLEMENTING FLEXIBLE LOGIC BLOCK LOGIC FOR EASY ENGINEERING CHANGES - A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). | 06-28-2012 |
20120180011 | Register Transfer Level Design Compilation Advisor - Techniques and tool for selecting compilation parameter values for compiling a first description of a circuit design, such as a register transfer language description, into a second description of the design, such as a model description for implementation with an emulator are provided. According to various examples of the invention, a compilation tool “elaborates” a first description of a circuit design into a third description for a circuit design. Typically, the third description or “elaboration” will cross one or more hierarchical boundaries represented in the first description of the design, so that the elaboration will represent at least a portion of two or more hierarchical modules in the first description design according to a non-hierarchical or “flat” manner. Also, with some implementations of the invention, the elaboration may include only a simple representation of the corresponding portion of the circuit design. For example, if the first description will be implemented on an emulator, then the elaboration may describe the primitive components that will be used for the emulation model, along with the interconnections between the primitive components. | 07-12-2012 |
20120180012 | RESET MECHANISM CONVERSION - Methods, circuits, and systems for converting reset mechanisms in a synchronous circuit design into a corresponding asynchronous representation are described. These may operate to convert synchronous state holding blocks that include reset signals to corresponding asynchronous dataflow logic blocks. A replicated reset token at a fraction of the operational frequency of the reset signal may be distributed to the locations of the asynchronous dataflow logic blocks. Additional methods, circuits, and systems are disclosed. | 07-12-2012 |
20120216159 | VERIFICATION TECHNIQUES FOR LIVENESS CHECKING OF LOGIC DESIGNS - A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop. | 08-23-2012 |
20120227020 | METHOD OF DETERMINING FET SOURCE/DRAIN WIRE, CONTACT, AND DIFFUSION RESISTANCES IN THE PRESENCE OF MULTIPLE CONTACTS - A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device. | 09-06-2012 |
20120233576 | SCHEMATIC-BASED LAYOUT MIGRATION - Method, system, computer, etc., embodiments receive an original integrated circuit design into a computerized device. The methods herein automatically replace at least some of the original cells within the original integrated circuit design with replacement cells using the computerized device. Each of the replacement cells has an initial cell size that is unassociated with any specific design size. The methods herein automatically change the original design size of the integrated circuit design to a changed design size, and automatically individually change the initial cell size of each of the replacement cells to different sizes. At least two different replacement cells are changed from the initial cell size by different size reduction amounts based on different amounts of space required within the changed design size for each of the replacement cells. | 09-13-2012 |
20120260224 | Digital Netlist Partitioning System For Faster Circuit Reverse-Engineering - Methods and systems are provided to reduce the complexity of sequential digital circuitry including cells of unknown function by grouping and defining like instance of combinational circuitry cells. The system groups together cells that feed into the same combination of one or more state cells. The groups of cells are then replaced by clouds which are defined in the netlist for the sequential digital circuitry to produce a simpler representation of the circuitry for analysis purposes and to aid in determining the function of those cells for which the function is unknown. | 10-11-2012 |
20120266117 | Logic Injection - A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object. | 10-18-2012 |
20120278772 | HARDWARE DEFINITION METHOD INCLUDING DETERMINING WHETHER TO IMPLEMENT A FUNCTION AS HARDWARE OR SOFTWARE - A hardware definition system and method includes a computer processor analyzing software function modules of a software program, and generating, for each of at least a subset of the software function modules, and on the basis of the analyzing step, a respective setting indicating whether the respective function module is to be implemented as a respective hardware module or as a software module executed on a hardware module defined in a hardware module library. | 11-01-2012 |
20120290992 | LOGICAL CIRCUIT NETLIST REDUCTION AND MODEL SIMPLIFICATION USING SIMULATION RESULTS CONTAINING SYMBOLIC VALUES - A logic synthesis program, method and system for simplifying and/or reducing a logic design receives output from a logic simulator that uses symbolic values for stimulus and contains symbolic values in the logic simulator output. Relationships between the nodes dependent on symbolic values can be used to merge nodes or otherwise simplify the logic design. Behaviors such as oscillators, transient values, identical signals, dependent logical states and chicken-switch determined states that depend on the symbolic values can be detected in the simulation results and the netlist simplified using the results of the detection. The netlist can be simplified by inserting registers to represent nodes that assume a symbolic value or combination based on symbolic values either statically or after an initial transient. Oscillating nodes can be replaced with equivalent oscillator circuits, and nodes having values dependent on chicken-switch operation can be detected and replaced with registers initialized from the chicken-switch input states. | 11-15-2012 |
20120331432 | IMPLEMENTING DUAL SPEED LEVEL SHIFTER WITH AUTOMATIC MODE CONTROL - A method and circuit for implementing a dual speed level shifter with automatic mode control, and a design structure on which the subject circuit resides are provided. A low speed level shifter and a high speed level shifter are used to provide a wide frequency range of operation. The circuit operates in one of a low speed mode or a high speed mode. The appropriate mode is selected automatically by detecting the frequency of the signal to be level shifted. When the incoming signal is slower than a reference frequency, the low speed level shifter is selected, and when the incoming signal is faster than the reference frequency, the high speed level shifter is selected. | 12-27-2012 |
20130024827 | SYSTEM AND METHOD FOR IDENTIFYING CIRCUIT COMPONENTS OF AN INTEGRATED CIRCUIT - A system and method for identifying circuit components of an integrated circuit includes a processor identifying geometric characteristics of an integrated circuit and sorting the geometric characteristics by order of occurrence of each geometric characteristic. Co-occurring arrangements of the geometric characteristics are then identified and used to identify a standard cell. The geometric characteristics of the standard cell may then be compared to the geometric characteristics of a known cell. Each electrically significant geometric characteristic of the standard cell can be compared to the electrically significant geometric characteristics of the known cell. If the standard cell matches the known cell an instance of the standard cell can be placed in a layout. Once placing the standard cell in the layout a netlist can be extracted. | 01-24-2013 |
20130024828 | SOLUTIONS FOR NETLIST REDUCTION FOR MULTI-FINGER DEVICES - A computer-implemented method for performing a layout extraction for a multi-fingered semiconductor device is disclosed. The method reduces the netlist for the device and the number of device fingers by identifying a set of device common nodes, and combining a plurality of parasitic elements in the device to form a set of representative parasitic elements which are connected to respective device common nodes. In one embodiment, the method includes: extracting a netlist for the multi-finger device which includes a plurality of parasitic elements identifying a set of common nodes; replacing the fingers of the multi-finger device with a new device having a width equivalent to the widths of the fingers of the multi-finger device; and combining the parasitic elements of at least one device common node into a single representative parasitic element which is representative of the original parasitic elements. | 01-24-2013 |
20130042214 | IIMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT - A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape. | 02-14-2013 |
20130047127 | METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES - Methods and apparatuses are disclosed for automatic relative placement of part of a clock tree in the course of generating a placed, routed, and optimized circuit design. | 02-21-2013 |
20130055174 | METHOD FOR VERIFYING FUNCTIONAL EQUIVALENCE BETWEEN A REFERENCE IC DESIGN AND A MODIFIED VERSION OF THE REFERENCE IC DESIGN - A method for verifying functional equivalence between a reference integrated circuit (IC) design and a modified version of the reference IC design includes simulating a reference IC design using a simulation stimulus on a test bench and saving the simulation output. The reference IC design corresponds to an IC design model having visibility to comprehensive internal device state. The method may also include simulating a modified version of the reference IC design using the same simulation stimulus on the same test bench, and saving the modified version simulation output. In addition, the simulation outputs of the reference IC design and the modified version are compared to create a comparison result. Lastly, the method may include determining whether the modified version of the reference IC design is functionally equivalent to the reference IC design based upon the comparison result. | 02-28-2013 |
20130055175 | SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist. | 02-28-2013 |
20130086537 | Design Routability Using Multiplexer Structures - Mechanisms are provided for generating a logic design of an integrated circuit device. An initial logic design representation of the integrated circuit device is received and one or more areas of the initial logic design representation are identified where logic elements in the one or more areas can be replaced with one or more multiplexer tree structures. Logic elements in the one or more areas of the initial logic design representation are replaced with multiplexer tree structures to generate a modified logic design representation. The modified logic design representation is output to a physical synthesis system to generate a physical layout of the integrated circuit device based on the modified logic design representation. | 04-04-2013 |
20130111423 | TOOL SUITE FOR RTL-LEVEL RECONFIGURATION AND REPARTITIONING | 05-02-2013 |
20130111424 | LOGICAL REPARTITIONING IN DESIGN COMPILER | 05-02-2013 |
20130117720 | COMPUTER PRODUCT FOR SUPPORTING DESIGN AND VERIFICATION OF INTEGRATED CIRCUIT - Design and verification support related to integrated circuits that includes acquiring a first use case diagram representing a function of an object subject to design and verification and an activity diagram representing a processing procedure of the object; analyzing a structure of the activity diagram acquired at the acquiring step; converting the activity diagram to a second use case diagram representing a function of the object, based on the structure analyzed at the analyzing; verifying uniformity of the first use case diagram and the second use case diagram; and outputting a verification result obtained at the verifying uniformity. | 05-09-2013 |
20130185683 | Method of Generating Integrated Circuit Model - An integrated circuit test model is generated according to a circuit connection net-list, an isolation cell topology, and a pin voltage information spec file, so that the procedure of generating the integrated circuit test model can be time-saving, efficient, and fool-proof. Besides, while tracing a current path of a node of the circuit connection net-list, the generated integrated circuit test model can be more precise if certain limitations are added. | 07-18-2013 |
20130191798 | CAPACITANCE EXTRACTION FOR ADVANCED DEVICE TECHNOLOGIES - A technology specific information to design the integrated circuit is received. A plurality of canonical hierarchical models to capture an integrated circuit capacitance are created. The plurality of canonical hierarchical models includes at least a canonical model to capture a capacitance of a device having a plurality of conductors, and a canonical model to capture a capacitance between at least a portion of the device and one or more other conductors of the integrated circuit. The canonical hierarchical models can be applied to a layout of the integrated circuit. A capacitance for the layout can be determined based on the canonical hierarchical models. | 07-25-2013 |
20130191799 | HIGH-LEVEL SYNTHESIS DEVICE, HIGH-LEVEL SYNTHESIS METHOD, HIGH-LEVEL SYNTHESIS PROGRAM, AND INTEGRATED CIRCUIT DESIGN METHOD - A high-level synthesis device, which converts a behavior description file describing a function of an integrated circuit using a high-level language without timing description, into a hardware description file describing the integrated circuit including timing description, has: a processor; a high-level synthesis unit in which the processor converts a behavior description file having a functional portion describing the function and a control portion controlling timing, into a first hardware description file; a variable extraction unit; a loop information generation unit; a static latency extraction unit; a latency calculation circuit generation unit in which the processor generates a second hardware description file describing a latency calculation circuit which generates the latency information based on loop count and static latency; and an insertion unit in which the processor inserts the second hardware description file into the first hardware description file to generate a third hardware description file. | 07-25-2013 |
20130198702 | IMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT - A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape. | 08-01-2013 |
20130205271 | MACRO TIMING ANALYSIS DEVICE, MACRO BOUNDARY PATH TIMING ANALYSIS METHOD AND MACRO BOUNDARY PATH TIMING ANALYSIS PROGRAM - A macro timing analysis device comprises a netlist merging unit which merges a layout-implemented top netlist obtained by executing clock path distribution and layout processing with respect to a top netlist with a lower-order hierarchy as a macro and a layout-implemented macro netlist obtained by cutting out a circuit in the macro from the layout-implemented top netlist to generate a merging-implemented macro netlist including description of a clock path outside the macro and description of a macro boundary path which are clock paths related to the macro, and a timing analysis unit which analyzes a timing of the macro boundary path by using the merging-implemented macro netlist. | 08-08-2013 |
20130227503 | DATA FLOW ANALYZER - A system and method for generating physical design of an integrated circuit, based on schematic design. The system includes graphical user interface and integrated circuit design and layout system. The integrated circuit design and layout system creates and analyzes logical slices of the integrated circuit based on the schematic design; creates and edits macros based on the logical slices; and traces and analyzes data paths through the physical design based on the schematic design. The method includes providing the schematic design of the integrated circuit, and generating logical slices of the integrated circuit from the schematic design. The method also includes generating, grouping and manipulating macros, responsive to identification of multiple occurrences of logical slices. The method further includes performing data flow analysis to identify data paths for the physical design, quantifying weight indices for the data paths, and positioning objects in the physical design based on the weight indices. | 08-29-2013 |
20130246985 | METASTABILITY EFFECTS SIMULATION FOR A CIRCUIT DESCRIPTION - A circuit design that contains at least two clock domains is simulated using a novel system and method for injecting the effects of metastability. The system includes detectors for detecting, during simulation, when a clock in a transmit clock domain and a clock in a receive clock domain are aligned and when the input of a register receiving a clock-domain-crossing signal is changing. The system includes coverage monitors for measuring, during simulation, statistics related to metastability injection. The system accurately models the effects of metastability by, at appropriate times during simulation, pseudo-randomly inverting outputs of registers receiving clock-domain-crossing signals. By accurately modeling the effects of metastability, errors in the circuit design can be detected while simulating a pre-existing simulation test. The simulation with metastability effects injection is repeatable and requires no modification of pre-existing RTL design files or simulation test files. | 09-19-2013 |
20130290917 | SYSTEM AND METHODS FOR INFERRING HIGHER LEVEL DESCRIPTIONS FROM RTL TOPOLOGY BASED ON CONNECTIVITY PROPAGATION - A system and several methods for inferring higher level descriptions of circuit connectivity from register transfer level (RTL) netlists in order to provide more understandable and manageable design descriptions for complex System-on-Chip (SOC) designs, is provided. In particular, interface matching based on connectivity propagation is automatically performed whereby port names and properties on instances of functional elements and blocks are propagated to top level design ports as well as other instances of functional elements and blocks to create a more robust description of connectivity according to the RTL netlist, and to automatically form signal groupings that comprise a higher-level abstracted description. Also, a facility is included to allow user-guided grouping of instantiated interfaces with respect to actual signal names and properties in an RTL-level design. | 10-31-2013 |
20130305197 | METHOD AND SYSTEM FOR OPTIMAL DIAMETER BOUNDING OF DESIGNS WITH COMPLEX FEED-FORWARD COMPONENTS - A computer-implemented method includes a processor identifying, within the netlist, at least one strongly connected components (SCCs) that has a reconvergent fanin input with at least two input paths from the reconvergent fanin input having a different propagation delay to the SCC. The method then computes an additive diameter for the netlist comprising at least one SCC, where the additive diameter includes a fanin additive diameter determined based on a propagation delay difference of the at least two input paths to a SCC and a number of complex feed-forward components within at least one input path. In response to the reconvergent fanin input to the SCC providing a binate function, the method computes a multiplicative diameter for the SCC utilizing a least common multiple (LCM) derived from one or more propagation delay differences across each reconvergent fanin input leading to the SCC. | 11-14-2013 |
20130311961 | TIMING EXACT DESIGN CONVERSIONS FROM FPGA TO ASIC - A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts. | 11-21-2013 |
20130326441 | MACHINE-LEARNING BASED DATAPATH EXTRACTION - A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster. | 12-05-2013 |
20130346927 | METHOD AND APPARATUS FOR SYNTHESISING A SUM OF ADDENDS OPERATION AND AN INTEGRATED CIRCUIT - A method is provided for a synthesising In RTL, a logic circuit and for manufacturing an integrated circuit for performing a sum of addends with faithful rounding. In this, optimisation constraints for a value of bits which may be discarded and a constant to include in a sum of addends are determined ( | 12-26-2013 |
20130346928 | METHOD FOR PROTECTING RTL IP CORE - A method for protecting Register Transfer Level (RTL) Intellectual Property (IP) core is provided, which converts an original RTL IP core to a target RTL IP core embedded with protection measures. The method includes: Step S1, constructing a state machine whose mode is controllable against the original RTL IP core, the state machine has a normal mode appeared corresponding to the normal function of the IP core after the entry of a correct preset secret key value and a fuzzy mode appeared corresponding to the abnormal function of the IP core after the entry of wrong secret key value; Step S2, revise the data flow of the RTL code in the original RTL IP core to obtain the fuzzy RTL code of the IP core; and Step S3: combine the state machine and the fuzzy RTL code into the targeted RTL IP core. By combining the secret key control and fuzzy data flow, the being embezzled and reverse-engineered of RTL IP core can be effectively prevented. | 12-26-2013 |
20140019921 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 01-16-2014 |
20140096094 | BREAKING UP LONG-CHANNEL FIELD EFFECT TRANSISTOR INTO SMALLER SEGMENTS FOR RELIABILITY MODELING - A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is created. In the degraded netlist, the first transistor is degraded by a device degradation for the first transistor. The second transistor is degraded by a device degradation for the second transistor. The circuit is re-simulated with the first degraded transistor and the second degraded transistor in place of the first MOS transistor. | 04-03-2014 |
20140109028 | Translating a User Design in a Configurable IC for Debugging the User Design - Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design. | 04-17-2014 |
20140129998 | HIERARCHICAL EQUIVALENCE CHECKING AND EFFICIENT HANDLING OF EQUIVALENCE CHECKS WHEN ENGINEERING CHANGE ORDERS ARE IN AN UNSHARABLE REGISTER TRANSFER LEVEL - An apparatus, a hierarchical method of equivalence checking a circuit design and equivalency checking after engineering change orders in a circuit design are disclosed herein. In one embodiment, a method of equivalence checking includes: (1) receiving a post-engineering change order (ECO) netlist of a first one of the functional blocks, wherein the post-ECO netlist has been verified employing an equivalence checker, (2) generating a top level netlist for the circuit design including the post-ECO netlist and a block netlist for a second one of the multiple functional blocks, (3) generating a top level register transfer level (RTL) for the circuit design including a RTL for the second functional block and (4) performing an equivalency check of the top level RTL to the top level netlist, wherein a RTL for the first functional block and the post-ECO netlist are black boxed for the performing. | 05-08-2014 |
20140129999 | METHOD FOR SELECTIVELY MODELING NARROW-WIDTH STACKED DEVICE PERFORMANCE - An approach for methodology enabling a verification of IC designs that compensates for degraded performance due to a physical placement, particularly a stacked physical placement is disclosed. A set of stacked devices from a plurality of devices in an IC design is determined. One or more instance parameters indicating a physical placement of a device in the set is determined. A compensation metric indicating one or more electrical characteristics of a device in the set is determined based on the one or more instance parameters. | 05-08-2014 |
20140143743 | Automated Circuit Design - A method implemented on a data processing system for circuit synthesis is discussed. In one embodiment, the method comprises determining a net of a circuit design, the net driving one or more first loads to use a first type of routing resources and one or more second loads to use a second type of routing resources, and splitting the net into a first net and a second net, the first net driving the one or more first loads, the second net driving the one or more second loads. | 05-22-2014 |
20140165015 | VECTORIZATION OF BIT-LEVEL NETLISTS - According to one aspect of the present disclosure, a method and technique for vectorization of bit-level netlists is disclosed. The method includes: receiving a bit-level netlist defining a plurality of registers; analyzing propagation of read data associated with the registers through logic of the bit-level netlist; and forming a plurality of vector-level bundles of registers based on the propagation of read data through the logic, wherein the plurality of vector-level bundles differ based on differences in references to memory arrays of the bit-level netlist by respective registers of the vector-level bundles. | 06-12-2014 |
20140173537 | METHODOLOGY FOR NANOSCALE TECHNOLOGY BASED MIXED-SIGNAL SYSTEM DESIGN - A method for designing complex, mixed signal circuits, comprising generating electronic data defining a baseline schematic design. Generating a parameterized parasitic-aware netlist using the baseline schematic design. Performing design and process parameter statistical optimization using the parameterized parasitic-aware netlist and mixed signal component specifications. Determining whether one or more predetermined design specifications are satisfied. Optimizing the parameterized parasitic-aware netlist if it is determined that the one more predetermined design specifications are not satisfied. Generating electronic data defining a schematic-optimal layout design if it is determined that the one or more predetermined design specifications are satisfied. | 06-19-2014 |
20140181764 | IDENTIFYING HIERARCHICAL CHIP DESIGN INTELLECTUAL PROPERTY THROUGH DIGESTS - One method implementation disclosed includes detecting matching leaf cells that have functionally identical designs (optionally, similar designs) and assigning matching names for the matching leaf cells to replace original, non-matching names. Optionally, digests can be calculated for the leaf cells and used to detect similarities and/or differences. The matching names are propagated to at least some higher-level cells in the hierarchical design, in place of the original names. The method can further include calculating digests for at least some of the higher level cells after the propagating of the matching names into the higher level cells. Various design matching technologies can be used in combination with cell renaming and new name propagation, not limited to use of digests. Dependency chains can be calculated to improve propagation of names through the hierarchy. | 06-26-2014 |
20140189620 | NETLIST ABSTRACTION - Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The embodiment can then create the netlist abstraction by, for each LH node in the set of LH nodes, replacing a portion of the netlist that is below the LH node by a star netlist, wherein the star netlist includes a center object that is electrically connected to a set of satellite objects, wherein each satellite object corresponds to a port of the LH node. | 07-03-2014 |
20140189621 | APPARATUS AND METHOD FOR MODELING CONTROLLER OF CAN BUS SIMULATOR - An apparatus and a method for modeling a controller of a CAN bus are provided. The apparatus for modeling a controller of a CAN bus includes a modeling device for modeling a communication unit of a controller of the CAN bus and for evaluating the communication unit in a configuration of a CAN bus topology of the CAN bus. The modeling device includes an evaluation item determiner for determining the evaluation item used for simulating the configuration of the CAN bus topology, a factor determiner for determining factors that affect the evaluation result of the determined evaluation items, and a circuit design device for designing the circuit configured to include the determined factors. | 07-03-2014 |
20140298277 | METHODS FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY - Various embodiments of methods of designing an integrated circuit (IC). One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) synthesizing a netlist from the functional IC design that meets the target clock rate, (4) determining a performance/power ratio from the netlist, (5) attempting to increase the performance/power ratio by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, and (6) implementing a layout of the IC from the netlist. | 10-02-2014 |
20140325460 | METHOD FOR SIMULATION OF PARTIAL VLSI ASIC DESIGN - A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs. | 10-30-2014 |
20140331194 | Method for manufacturing a chip from a system definition - A method for manufacturing a chip from a system definition, the system definition describing a plurality of cells, buses and external I/O. The cell definitions are defined by providing two libraries, a first containing a superset of cell definitions; and a second a plurality of HDL definitions of cells selected from the first library. The method further included creating the system definition from the second library, a bus definition, and an external I/O definition. | 11-06-2014 |
20140337810 | MODULAR PLATFORM FOR INTEGRATED CIRCUIT DESIGN ANALYSIS AND VERIFICATION - A modular electronic design automation tool platform for analyzing and verifying an integrated circuit design. The platform may provide a single, unified database that can contain both logical information and physical information relating to an integrated circuit design, together with a plurality of electronic design automation operation execution modules for performing one or more desired electronic design automation operations. The platform may also provide export modules and import modules. An export module extracts relevant data from the database, and configures that data for use by a specific electronic design automation operation execution module. An import module then receives output data from a particular electronic design automation operation execution module, configures that data for integration into the unified database, and then imports the configured data into the database. | 11-13-2014 |
20150020038 | Method for Efficient FPGA Packing - A method for programming a cluster-based field programmable gate array (FPGA) device includes providing a netlist and cluster size information, translating the netlist into a hypergraph, partitioning the hypergraph into multiple partitions and optimizing the Rent characteristic, translating the partitions into clusters, placing the clusters on the FPGA device, routing interconnects using a pre-fabricated routing resource on the FPGA device, generating a programming bitstream in response to the placing and routing, and providing the programming bitstream to the FPGA device to realize the user design. | 01-15-2015 |
20150074623 | USER GREY CELL - In various embodiments, a user grey cell is disclosed. The user grey cell comprises a simplified logical implementation of a black box cell identified in a software and/or hardware design. The internal functionality of the black box cell is undefined, hidden, or encrypted, and thus is not available for timing analysis. The user grey cell for the black box cell provides sufficient clocking and register information to allow for accurate CDC, false path, and multi-cycle path analysis, and provides a way for designers to locate and repair clock domain crossing violations before the design is implemented in hardware. In various embodiments, a method for user grey cell analysis is disclosed. The method comprises identifying one or more black box cells in a user design. The method further comprises determining which of the input and/or output pins of each of the black box cells are in use by the user design. The method further comprises selecting a user grey cell for one or more of the black box cells, wherein a user grey cell comprises a simplified logic implementation for the black box cell, sufficient to perform CDC, false path, and multi-cycle path analysis. The selected user grey cells may be used in place of the black box cells for CDC, false path, and multi-cycle path analysis. | 03-12-2015 |
20150095860 | METHOD FOR ARRANGING AND WIRING RECONFIGURABLE SEMICONDUCTOR DEVICE, PROGRAM THEREFOR, AND ARRANGING AND WIRING APPARATUS - An arrangement and wiring method of a reconfigurable semiconductor device, including: generating a net list based on a circuit description in which a circuit configuration is described; extracting a sequential circuit data set which is to be scanned from the net list; generating a first truth value table data set so as to write into a first set among plurality of memory cell units from the sequential circuit data set which is to be scanned; and generating a second truth value table data set so as to write into a second set among the plurality of memory cell units from a combination logic circuit data set of the net list. | 04-02-2015 |
20150095861 | METHOD FOR PRODUCING A DPA-RESISTANT LOGIC CIRCUIT - In an application-specific integrated circuit (ASIC), a description of the logic circuit is formulated in a hardware description language and then converted into a description of a corresponding physical circuit, i.e., into a netlist, using a conversion program, i.e., a synthesis tool. The description at least largely consisting of standard cells. During the conversion process, the standard cells which are used in the netlist are replaced with standard cell versions which have a correspondingly balanced power dissipation. Spying on a mode of operation of the circuit by analyzing a power consumption of the circuit is thus advantageously hindered or prevented, in particular in security-relevant circuits. | 04-02-2015 |
20150100929 | REVERSE SYNTHESIS OF DIGITAL NETLISTS - A method and method of extracting information from a netlist. The netlist for a device under test (DUT) is read and a circuit selected to be transformed. Transformation candidates are identified using transformation specific criteria and verification methods are applied to prove the transformation is equivalent to the circuit being transformed. If the candidate transformation is equivalent to the circuit being transformed, the system commits to the transformation. If the candidate transformation is not equivalent to the circuit being transformed, the transformation is undone. | 04-09-2015 |
20150121322 | CIRCUIT DESIGN PORTING BETWEEN PROCESS DESIGN TYPES - Among other things, one or more systems and techniques for porting a circuit design from a first process design type to a second process design type are provided. A circuit design comprises one or more components, such as transistors, that are arranged and sized according to a first process design type, such as a 90 nm processing environment. The circuit design is partitioned into one or more topology categories such as a current mirror topology category or a differential pair topology category. Ordered sets of parameters are determined for respective topology categories. The components within the circuit design are resized based upon the one or more topology categories to generate a ported circuit design specified for the second process design type, such as a 50 nm processing environment. | 04-30-2015 |
20150121323 | DETERMINING A QUALITY PARAMETER FOR A VERIFICATION ENVIRONMENT - Determining a quality parameter for a verification environment for a register-transfer level hardware design language description of a hardware design. A netlist is generated from the hardware design language description. A list of hardware design outputs is generated, and logical paths in the netlist are generated based on the list of hardware design outputs. Furthermore, a modified netlist involving logical paths is generated by determining whether a gate is selected as an insertion point, and selecting a fault type, which is part of the efficiency vector for the selected gate in the netlist and inserting a mutant. Additionally, a fault simulation is performed and the quality parameter for the verification environment is determined from the fault simulation and the simulation result data. | 04-30-2015 |
20150324505 | COMPUTER IMPLEMENTED SYSTEM AND METHOD OF TRANSLATION OF VERIFICATION COMMANDS OF AN ELECTRONIC DESIGN - A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation. | 11-12-2015 |
20150331983 | METHOD FOR AUTOMATICALLY GENERATING A NETLIST OF AN FPGA PROGRAM - A method for generating a netlist of an FPGA program. The model of the FPGA program is composed of at least two components, each component being assigned a separate partition on the FPGA. An independent build is carried out for each component and an overall classification is generated from the components, wherein the build jobs are automatically started after a trigger event and the trigger event is a saving of a component, the exiting of a component of the design, or a time-controlled, automated initiation of a build. | 11-19-2015 |
20150339414 | METHOD FOR PROCESS VARIATION ANALYSIS OF AN INTEGRATED CIRCUIT - A method and a corresponding system for process variation analysis of an integrated circuit are provided. A netlist is generated describing electronic devices of an integrated circuit in terms of device parameters and process parameters. The process parameters include local process parameters individual to the electronic devices and global process parameters common to the electronic devices. Critical electronic devices are identified having device parameters with greatest contributions to a performance parameter of a design specification of the integrated circuit. Sensitivity values are determined for the global process parameters and local process parameters of the critical electronic devices. The sensitivity values represent how sensitive the one or more performance parameters are to variations in the global and local process parameters of the critical electronic devices. Monte Carlo (MC) samples are sorted based on the sensitivity values. | 11-26-2015 |
20150363517 | TECHNIQUES FOR GENERATING PHYSICAL LAYOUTS OF IN SILICO MULTI MODE INTEGRATED CIRCUITS - This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing. | 12-17-2015 |
20150379183 | SYSTEM AND METHOD FOR HYBRID CLOUD COMPUTING FOR ELECTRONIC DESIGN AUTOMATION - Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data. | 12-31-2015 |
20160019332 | Interposer Defect Coverage Metric and Method to Maximize the Same - A method includes receiving a design of an interposer having nets, probe pads, and micro-bumps. The nets connect the micro-bumps. The probe pads are initially unconnected to the nets. The method further includes initializing a first set to logically include the nets; processing the first set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two micro-bumps are interconnected by one net; calculating an untested length for each net in the first set; selecting a net N from the first set wherein the net N has the maximum untested length in the first set, the net N representing at least a portion of a net P of the nets; selecting a pair of probe pads that are unconnected to the nets; and connecting the pair of probe pads to the net P by two dummy nets. | 01-21-2016 |
20160026749 | INTEGRATED CIRCUIT LAYOUT DESIGN SYSTEM AND METHOD - A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns. | 01-28-2016 |
20160034628 | SYSTEM, METHOD AND COMPUTER-ACCESSIBLE MEDIUM FOR PROVIDING SECURE SPLIT MANUFACTURING - Exemplary systems, methods and computer-accessible mediums can secure split manufacturing of an integrated circuit by modifying a previous location of at least one pin to a further location of the at least one pin based on a fault analysis procedure. A determination of the further location can include an iterative procedure that can be a greedy iterative procedure. The modification of the location of the at least one partition pin can be performed by swapping at least one further partition pin with the at least one partition pin. | 02-04-2016 |
20160063165 | CELL BASED HYBRID RC EXTRACTION - One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a 3D RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5D RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell. | 03-03-2016 |
20160085903 | COMPUTER BASED SYSTEM FOR VERIFYING LAYOUT OF SEMICONDUCTOR DEVICE AND LAYOUT VERIFY METHOD THEREOF - There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout. | 03-24-2016 |
20160125102 | RECIPROCAL QUANTUM LOGIC (RQL) CIRCUIT SYNTHESIS - One embodiment of the invention includes a method for generating a Reciprocal Quantum Logic (RQL) circuit design via a synthesis tool. The method includes providing data associated with behavior and constraints of the RQL circuit design and a component library to the synthesis tool. The method also includes generating an RQL netlist circuit comprising a flip-flop device placeholder and a circuit system coupled to at least one of an input and an output of the flip-flop device placeholder via the synthesis tool based on the data and a component library. The method also includes separating the circuit system into circuit subsystems that are each associated with a separate respective phase of a clock signal via the synthesis tool based on inputs. The method further includes removing the flip-flop device placeholder from the RQL netlist circuit via the synthesis tool to generate the RQL circuit design from the RQL netlist circuit. | 05-05-2016 |
20160125109 | Polymorphic Circuit Simulation System - A method for operating a data processing system to simulate a circuit that includes a plurality of circuit devices connected by interconnects. A layout description of the circuit is provided in which the devices are connected by interconnects. Each interconnect is associated with a line definition that includes a physical description of an interconnect between two of the circuit devices and a simulation model to be used in simulating the interconnect during simulations of the circuit. The line definitions are user selectable from a list of available line definitions. A circuit netlist is generated by reading physical interconnects from the layout. At least one of the interconnects is replaced by a plurality of transmission line devices, each device being associated with the simulation model included in the line definition. The circuit is then simulated using the netlist. | 05-05-2016 |
20160140271 | INTEGRATED CIRCUIT MODELING METHOD - A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification. | 05-19-2016 |
20160140276 | 3D CIRCUIT DESIGN METHOD - The invention concerns a 3D circuit design method implemented by a processing device involving partitioning a 2D circuit representation into two or more tiers, the 2D circuit representation defining circuit elements interconnected by interconnecting wire each weighted based on at least one of: its length; its propagation delay; and its priority level, the 2D circuit representation initially forming a first tier, the partitioning involving: a) selecting a first highest ranking wire, interconnecting at least first and second circuit elements in the first tier; b) moving one of the first and second circuit elements connected by the selected wire to a further tier of the 3D circuit representation and replacing the interconnecting wire with a connecting via between the first and further tiers; and c) repeating a) and b) for one or more further interconnecting wires of the first tier. | 05-19-2016 |
20160147924 | Handling Blind Statements In Mixed Language Environments - This application discloses a computing system configured to determine that a first bind command is configured to prompt instantiation of an assertion module in a target module of a circuit design, which creates a mixed-language environment for the circuit design. The computing system, in response to the determination that the first bind command is configured to create the mixed-language environment for the circuit design, configured to generate a wrapper module configured to prompt instantiation of the assertion module in the wrapper module. The computing system configured to generate a second bind command configured to prompt instantiation of the wrapper module in the target module. | 05-26-2016 |
20160181092 | NITRIDE SPACER FOR PROTECTING A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE | 06-23-2016 |
20180025100 | Method and Apparatus for Improving System Operation by Replacing Components for Performing Division During Design Compilation | 01-25-2018 |